Most of the computer's instructions tell it to perform a particular basic arithmetic calculation. The form of these instructions, in the mode of operation of the computer chosen as the most straightforward for introducing its instruction set, is shown below:
The dR and sR fields, giving the destination register and the source register for an operation, can contain any value from 0 to 7. The sB field, indicating the base/address register whose contents indicate the general area in memory from which a memory operand comes, can only contain a value from 1 to 7; this distinguishes the latter two formats in the diagram from the first one. Similarly, the sX field, which indicates the arithmetic/index register whose contents are used to select the element of an array used as a memory operand, can only contain a value from 1 to 7; this distinguishes the third format in the diagram from the second one. The convention used in this diagram, that a zero field in an instruction indicates that the same field must be nonzero in instruction formats below it not otherwise distinguished by opcode bits, but has no effect on fields above it, is followed in diagrams elsewhere in these pages as well.
The first two bits of the seven-bit opcode shown in the instruction may be 00, 01, or 10. Instructions starting with 11 are used for other instructions needed by the computer, such as instructions used to transfer control from one part of a program to another.
The opcode is divided into two parts: the first part indicates the type of number the instruction works with:
000 Byte 8-bit integer 001 Halfword 16-bit integer 010 Integer 32-bit integer 011 Long 64-bit integer 1000 Medium 48-bit floating-point 1001 Floating 32-bit floating-point 1010 Double 64-bit floating-point 1011 Quad 128-bit floating-point
and the second part indicates the operation performed by the instruction:
0000 000 Swap 0001 001 Compare 0010 010 Load 0011 011 Store 0100 100 Add 0101 101 Subtract 0110 110 Multiply 0111 111 Divide 1000 Insert 1001 Unsigned Compare 1010 Unsigned Load 1011 XOR 1100 AND 1101 OR 1110 Multiply Extensibly 1111 Divide Extensibly
The first eight operations apply both to floating-point numbers and integers; the second eight operations apply only to integers.
Integer operations working with long, or 64-bit integers, have as their destination a pair of registers, beginning with an even-numbered register. The location of an operand in memory can begin with any byte, as addresses are byte addresses, but there may be a performance penalty if an operand is fetched from an unaligned location. In the case of floating-point numbers of the medium type, 48 bits in length, an aligned operand is one that begins on the boundary of a unit of 16 bits; for other types, an aligned operand is one whose address is an integer multiple of its length in bytes, so that all memory could be evenly divided into units of that length with no bytes left over at the beginning or the end. Note that it may be attempted by an implementation to fetch more than 16 bits of a medium floating-point number in a single operation, in which case a performance penalty may be experienced on aligned operands on this type which cross a block boundary; the rules for this would be both more complicated and implementation-dependent.
For integers shorter than 32 bits, the insert and unsigned load instructions are used as possible alternatives to the load instruction. The difference between the three instructions is as follows:
The load instruction performs sign extension. A quantity loaded into a 32-bit register is loaded into its rightmost, or least significant, bits, and the first bit of that quantity is also used as the value to which to set all the bits to the left of those filled by the quantity. This ensures that a negative number represented in a variable occupying less than 32 bits of memory is converted to the same negative number in 32-bit form.
The unsigned load instruction fills the bits to the left of the number with zeroes. This allows using variables to represent positive numbers only, and recovering the use of the first bit to allow larger positive numbers to be represented.
The insert instruction does not alter the bits to the left of the number. This allows a 32-bit number to be built up out of smaller pieces.
Other instructions that may need some explanation are as follows:
The compare instruction sets certain status bits in the same way that an ideal subtraction would set them. That is, the status bits indicate "negative" if the destination is less than the source, "zero" if they are equal, and "positive" if the destination is larger than the source, even if performing an actual subtraction for the same argument type would result in an overflow.
The unsigned compare instruction treats its operands as unsigned numbers, since this makes a difference in what the result of a comparison would be, even though two's complement representation means that a subtraction produces the same resulting pattern of bits in both cases.
The multiply extensibly instruction has a destination which is as long as the source on entry, but twice as long as its source on exit. This means that it produces a double-length product of two values, allowing it to be used in performing multi-precision arithmetic.
The divide extensibly instruction has a destination which is twice as long as the source on entry, and which consists of two consecutive registers, or groups of registers, the first twice as long as the source, and the second as long as the source, on exit. It divides the destination by the source, and places the quotient in the first part of the destination, while leaving the remainder in the second, shorter, part of the destination.
Note that because not only the dividend, but also the quotient, is twice as long as the divisor and the remainder with this instruction, the condition known as a "divide check", where a large dividend and a small divisor results in a quotient that will not fit into the result field on exit cannot occur.
The other instructions are self-explanatory.
The swap instruction exchanges the contents of the source and destination.
Add, subtract, multiply, and divide perform the indicated operation, producing results of the same type as their operands.
AND, OR, and XOR perform the basic logical operations:
a b a AND b a OR b a XOR b -------------------------------------- 0 0 0 0 0 0 1 0 1 1 1 0 0 1 1 1 1 1 1 0
in a bitwise fashion on their operands, storing the result in the destination.
A store instruction takes the value at the location specified by the destination field, and stores it at the location specified by the source field. By reversing the normal uses of destination and source, it allows values in registers to be written back out to memory.
Not all the possible combinations of the bits shown above are valid instructions. The Insert and Unsigned Load instructions only apply to byte and halfword operands. Also, Multiplication and division are not provided for byte operands. Instead, the instruction that would have been Divide Extensibly Byte is Store if Greater Byte: this instruction compares the destination byte (which is in a register) to the source byte (which may be in memory), and if the source byte is less than the destination byte, the byte at the destination is copied to the source location, overwriting its contents. This specialized instruction is used to allow semaphores to be used to control the sharing of resources between processes.
Thus, the seven bit opcodes that are defined are as follows, when their mnemonics are shown in a compact tabular form:
0000 0001 0010 0011 0100 0101 0110 0111
SWB IB SWH IH SW SWL 000
CB UCB CH UCH C UC CL UCL 001
LB ULB LH ULH L LL 010
STB XB STH XH ST X STL XL 011
AB NB AH NH A N AL NL 100
SB OB SH OH S O SL OL 101
MH MEH M ME ML MEL 110
STGB DH DEH D DE DL DEL 111
1000 1001 1010 1011
SWM SWF SWD SWQ 000
CM CF CD CQ 001
LM LF LD LQ 010
STM STF STD STQ 011
AM AF AD AQ 100
SM SF SD SQ 101
MM MF MD MQ 110
DM DF DD DQ 111
and listed in full, they are:
000xxx SWB Swap Byte 001xxx CB Compare Byte 002xxx LB Load Byte 003xxx STB Store Byte 004xxx AB Add Byte 005xxx SB Subtract Byte 010xxx IB Insert Byte 011xxx UCB Unsigned Compare Byte 012xxx ULB Unsigned Load Byte 013xxx XB XOR Byte 014xxx NB AND Byte 015xxx OB OR Byte 017xxx STGB Store if Greater Byte 020xxx SWH Swap Halfword 021xxx CH Compare Halfword 022xxx LH Load Halfword 023xxx STH Store Halfword 024xxx AH Add Halfword 025xxx SH Subtract Halfword 026xxx MH Multiply Halfword 027xxx DH Divide Halfword 030xxx IH Insert Halfword 031xxx UCH Unsigned Compare Halfword 032xxx ULH Unsigned Load Halfword 033xxx XH XOR Halfword 034xxx NH AND Halfword 035xxx OH OR Halfword 036xxx MEH Multiply Extensibly Halfword 037xxx DEH Divide Extensibly Halfword 040xxx SW Swap 041xxx C Compare 042xxx L Load 043xxx ST Store 044xxx A Add 045xxx S Subtract 046xxx M Multiply 047xxx D Divide 051xxx UC Unsigned Compare 053xxx X XOR 054xxx N AND 055xxx O OR 056xxx ME Multiply Extensibly 057xxx DE Divide Extensibly 060xxx SWL Swap Long 061xxx CL Compare Long 062xxx LL Load Long 063xxx STL Store Long 064xxx AL Add Long 065xxx SL Subtract Long 066xxx ML Multiply Long 067xxx DL Divide Long 071xxx UCL Unsigned Compare Long 073xxx XL XOR Long 074xxx NL AND Long 075xxx OL OR Long 076xxx MEL Multiply Extensibly Long 077xxx DEL Divide Extensibly Long 100xxx SWM Swap Medium 101xxx CM Compare Medium 102xxx LM Load Medium 103xxx STM Store Medium 104xxx AM Add Medium 105xxx SM Subtract Medium 106xxx MM Multiply Medium 107xxx DM Divide Medium 110xxx SWF Swap Floating 111xxx CF Compare Floating 112xxx LF Load Floating 113xxx STF Store Floating 114xxx AF Add Floating 115xxx SF Subtract Floating 116xxx MF Multiply Floating 117xxx DF Divide Floating 120xxx SWD Swap Double 121xxx CD Compare Double 122xxx LD Load Double 123xxx STD Store Double 124xxx AD Add Double 125xxx SD Subtract Double 126xxx MD Multiply Double 127xxx DD Divide Double 130xxx SWQ Swap Quad 131xxx CQ Compare Quad 132xxx LQ Load Quad 133xxx STQ Store Quad 134xxx AQ Add Quad 135xxx SQ Subtract Quad 136xxx MQ Multiply Quad 137xxx DQ Divide Quad
Note that when the base register field of an instruction is zero, this indicates that the instruction specifies an operation between two registers rather than an operation involving memory, and, for instructions that refer to memory, when the index register field of an instruction is zero, indexing does not take place.
In a register-to-register instruction, the source and destination registers must be different. When these two fields contain the same number, the instruction is instead decoded to provide an instruction with an advanced addressing mode, for such things as vector operations, or to provide an exotic operate instructions. (The more straightforwards operate instructions will be discussed in the next section, such as the jump instruction, the shift instructions, and memory-reference instructions for packed decimal and character-string types.)