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Interpretive Execution: Code 12 Microprograms

When the DET instruction is used with code 12, it defines the description of a conversion to be applied to items retrieved from successive locations in data memory which will then be submitted to the main logic of the computer for execution; as well, a table in program memory will contain the converted instructions so that, under appropriate circumstances, these converted instructions can be reused.

For the EET instruction under code 12, the L bit must be a 1, and the length field represents both the number of entries in the table of converted instructions as a power of two (zero means one entry, one means two entries, and so on) and the size of the source operand, which is the program to be executed under emulation. The unit of alignment for instructions being emulated, and the size of entries in the table of converted instructions are defined in the translate program itself. The T bit must be a 1, as the table of converted instructions is treated as the translate table argument to the instruction. The D and A bits must be 0. In the corresponding DET instruction, the bits must be set the same way as well.

The type field in the EET and DET instructions is instead used to indicate the data memory width in use for the source operand, which need not be the same as the data memory width currently set in the Program Status Quadword. As with the general form of the EET and DET instructions, these bits, in addition to the four-bit microprogram number, are used to link definitions created by a DET instruction with their execution in an EET instruction, so up to 16 different interpretation layouts may be defined for each width value setting.

The first bit of the type field indicates, if 0, that the default character size is used when the execution unit is fed a character instruction, and if 1, that the alternate character size is used. The dSize field indicates the word length to be used for the data memory in which the simulation is being performed, and the significance of these bits is as follows:

dSize       def alt
00 32 bits   8  ---
01 40 bits  10   8
10 24 bits   6   8
11 36 bits   9   6

Whether or not the default character size is used for executed instructions, it is always used for program code fetching.

Also, when the EET instruction is executed, the register indicated by the aX field in the instruction serves as the program counter for the simulated program under execution, in units of default-size characters, except for its most significant bit, which, when set, causes the converted instruction table to be cleared on entry to the instruction, and that bit to be cleared as well.

In addition, the three bits of the dX field have the following significance:

Thus, the format of an EET instruction for code 12 microprograms is, in effect, the following:

Note also that while the EET instruction does provide for various modes in which only partial function of the instruction can be selected, one useful mode of partial operation is not initiated by means of an EET instruction: filtering of data types only, while execution proceeds normally. This is instead invoked by setting the relevant bits of the Program Status Quadword directly, possibly by an SLSFUM instruction.

The format of a code 12 interpretation layout is as follows:

The first 16 bits of a code 12 microprogram give the total length of the microprogram in 16-bit halfwords, as with a code 0 microprogram.

In the second halfword, the sSize field gives the number, less one, of default-size characters that are to be provisionally fetched for instruction decoding; this is normally the length of the longest possible instruction. (A default-size character is 6 bits in length for a 24 bit word, 9 bits in length for a 36 bit word, and 10 bits in length for a 40 bit word.) The tSize field gives the number of instruction alignment units (halfwords unless a variant alignment mode is specified), less one, that are to be allocated to converted instruction code in the translated code table.

The translated code table consists of two elements: the first consists of a one byte entry for each location in the table, and the second is the converted instructions themselves. As long as the table has at least sixteen entries, if the table begins on an aligned location, the portion containing the actual converted instructions will also be aligned even to 128-bit boundary.

Each of the one-byte entries in the first part of the table answers the questions:

If the answer to the final question is yes, then if an instruction is interpreted at the address in question is part of self-modifying code, and must be re-decoded whenever it is executed. Otherwise, the translated code table is used to avoid repeating the translation of instructions.

As for external subroutine branches, it is expected that most, but not necessarily all, instructions of a computer being simulated can be simulated by the execution of one or two native machine instructions. In the case of an external subroutine branch, the table contains the address of a subroutine to be called which executes in the same addressing mode as the computer was in when the EET instruction was executed. This causes an exit from the EET instruction; the return address of the implied subroutine jump is that of the EET instruction itself, which can resume because the simulated program counter is externally stored.

Because an external subroutine call constitutes an exit from the EET instruction, it is not necessary for the subroutine to return to the EET instruction; advancing the return address will permit exit from a simulated program.

The capabilities of a code 12 interpretation layout are such that instead of being executed as a microprogram, it can be used for specifying how dedicated logic is organized. Thus, while a DET instruction is likely to be implemented by a microprogram, so as to convert the supplied interpretation layout (also termed a code 12 microprogram) into an efficient internal form, it is intended that the interpretation initiated by the EET instruction be executed as rapidly as possible.

Because the capabilities of instruction conversion are limited, external subroutines will be needed to handle such things as decimal operands that are bounded by delimiter codes instead of a length field in the instruction, and branches to the last element of an instruction (with a flag bit, for example, indicating where the instruction begins) rather than the first. Thus, this emulation assist feature, although it covers a significant range of architectures, is still not universal in scope.

The format of the one-byte entries in the first part of the translated code table is:

The first bit, I, is set when an instruction was translated to provide an entry in the table.

The second bit, M, is set, whether or not the I bit is set, when the simulated program itself stores data in the location corresponding to the table entry.

The third bit, C, is set for any subsequent table entries corresponding to the remaining portions of an instruction translated into the table entry corresponding to the first part of an instruction. This flags unused table entries for the simulation of architectures with variable-lengh instructions, and allows propagating the setting of the M bit backwards when storage has taken place to a location from which an instruction had already been taken and converted.

The fourth bit, S, is set if an instruction was translated to the address for an external subroutine call rather than to machine code.

The length field, which contains a number from 0 to 15, indicates the number of instruction alignment units filled with the code to which the current instruction is converted. If 16 alignment units have been allocated to each table entry, 0 indicates all 16 are used; if more than 16 alignment units have been allocated, a 0 indicates that the first alignment unit contains the number of alignment units used.

The R bit indicates that when an instruction directly fed to the execution unit calls for a packed decimal number of fixed length for use with the arithmetic/index registers, that is, a register packed instruction, a translation routine will be applied to that operand.

The P bit indicates the same for the regular packed decimal operands of the memory-to-memory packed decimal instructions.

The S bit indicates that when an instruction directly fed to the execution unit calls for a simple floating-point number, a translation routine should be applied to the floating-point operand as well. Separate translation routines are required for load and store.

The F bit indicates the same for regular floating-point numbers.

In the third halfword, the V bit and the mode field indicate, when instructions are directly fed to the execution unit by means of simulation, what addressing mode is to be applied to them; the V bit indicates a variant alignment mode. General register mode, a variant alignment mode, particularly lends itself to emulation use.

The aShift field indicates how many places left an address, as used by the simulated program, needs to be shifted to become a default character address; this avoids having to edit address fields in instructions and avoids complexities when integer arithmetic and indexing are combined.

A code 12 microprogram is divided into sections. The first section, always present, handles the translation of instructions. Remaining sections, if required, translate simple floating and floating operands.

The L bit in the section header is zero for the header of all sections except the last.

The ten bit nLevels field indicates the number of levels in the current section.

For sections other than the first, the D bit, if 1, indicates the section provides translation for storage as opposed to fetching; the S bit that the simple floating-point format is being processed, the F bit that the regular floating-point is being processed. If either the F bit or the S bit is set, the two bits marked R and P indicate the applicable precision (for floating: 00: medium, 01: floating, 10: double, 11: quad; for simple: 01: halfword, 10: word, 11: long); otherwise, the bit marked P indicates that the description of how to process a regular packed decimal operand follows, and the bit marked R indicates that the description of how to process a packed decimal operand of the type used in the register-based packed decimal instructions follows.

A level defines one translation step in the processing of an instruction or operand. Each level consists of one or more stages, which specify how some bits in the operand are to be processed; all the stages in a level effectively execute in parallel, and the output from the level is the OR of the outputs of all the stages which make it up. After the transformation specified in a level is completed, the result is either used directly, or another level is then applied to the intermediate result.

The L bit in a level header is zero except for the last level in a section. The nLevel field identifies the level currently being defined. The 5-bit nStages field indicates the number of stages that make up the definition of this level. The nAdvance field, if nonzero, specifies the length of the source instruction being simulated; if zero, this is either specified in a translate table in one stage of this level, or in another level.

Actual operations on the instruction words or data words are specified within the stages. Again, a stage header begins with an L bit zero except in the last stage in a level. The V bit indicates that a signed displacement is either added to or subtracted from the bit string being processed; this is useful for floating-point format conversion; the disp field contains that displacement.

The nStage field indicates which stage is being defined.

If the A bit is one, this stage will, through a translate table entry, specify the length of the source instruction. If the D bit is one, this stage will, through a translate table entry, specify the level to be performed after this level. If the T bit is one, the bits taken from the positions indicated in the input mask, and then placed in order in the positions indicated in the output mask, will first, considered as a contiguous string of bits, be translated using a translate table.

The iLength field indicates the length of the input to this stage (and should be consistent across a level); this length is in halfwords, as it specifies the mask length. (The sSize field in the program header specifies the actual length of what is fetched, and will be treated as left-aligned in the first level.)

The tLength field indicates the number of bits that are set in the input mask, giving the number of entries in the translate table as a power of two.

The oLength field indicates the length of the output of this stage in halfwords, and the length of the output mask.

The eLength field indicates the number of halfwords of data in a translation table entry.

Each translate table entry begins with a halfword containing an F bit, to indicate if the output (if the table is in the last level, and instructions are being translated) is the address of an external subroutine instead of an instruction; an nAdvance field, which, if the A bit is set in the stage header, defines the length of the instruction being simulated for purposes of advancing the program counter; and an nLevel field, which, if the D bit is set in the stage header, specifies the next level to use after the current level.

The bits in the remaining halfwords of the entry, which contain the actual data to be output from the translation, are considered to be left-aligned, so that an arbitrary number of bits may be set in the output mask. (When no translation table is specified, the number of bits set in the input mask and in the output mask should be equal.)

Stages follow each other immediately; each level is terminated with a level exit header and each section is terminated with a section exit header.

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