Opcodes are available for some mode-independent instructions:
170mnn SETAM Set Addressing Mode (m = 4,5,6,7) 17140n SETPT Set Primary Type 17141n SETST Set Secondary Type 17142m SPSITTM Set Primary/Secondary Instruction Type Tracking Mode (m = 0,1,2,3) 1714mn SETT Set Type (m = 4,5,6,7) 17150n FLL Fixed-Length Loop 171510 CPS Compose Pipeline Sequence 17152n REP Repeat 171530 RMOI Register Multiple Operand Instruction 1716mn OST Override Storage Type (m = 0,1) 17162n SETOTM Set Opcode Translation Mode 171750 SPC Switch Program Counter 171752 SPCAN Switch Program Counter After Next 171753 SPCIB Switch Program Counter If Branch 171754 INUAF Interpret Next Using Alternate Formats 171756 SNF Switch to Normal Format 171757 SSF Switch to Secondary Format 171772 FCBPT Flag Conditional Branch as Preferably Taken 171773 FCBPNT Flag Conditional Branch as Preferably Not Taken 171774 SUSIUM Set User Status Immediate Under Mask 171775 SSIUM Set Status Immediate Under Mask 171776 0mmmmm SSFUM Set Status Field Under Mask 1724nn SVC Supervisor Call 1726mn SETPW Set Primary Width (m = 0,1,2,3) 1726mn TSETPW Temporarily Set Primary Width (m = 4,5,6,7) 1727mn SETSW Set Secondary Width (m = 0,1,2,3) 1727mn TSETSW Temporarily Set Secondary Width (m = 4,5,6,7) 173mnn INWM Interpret Next With Mode (m = 4,5) 1736mn SLSFUM Set Long Status Field Under Mask (m = 0,1,2,3) 1737nn (Supplementary Instruction)
by making use of unused opcode space related to that used by the shift instructions, specifically the instructions of the form 17abxx, where the a stands for an octal digit whose binary form is 0xx, and the b stands for an octal digit whose binary form is 1xx.
These instructions are only fully mode-independent for the modes with 16-bit alignment with the exception of Advanced Compound Mode. Opcode space is not reserved for these instructions with their normal opcodes in that mode, as it is intended to serve as a complete re-examination of the entire instruction set of the computer, possibly making all other instruction modes unnecessary. When the variant alignment bit is set, these instructions cease to be independent of the addressing mode, but they may still be available to a limited extent, and in a modified form, from some of the modes with other instruction alignments. Only SVC, SETPT, SETST, SPSITTM, SETT, SETOTM, SPC, SPCAN, SETFIT, SETFLT, SPCIB, SETW, SETAM, and SUSIUM, which are the 16-bit long mode-independent instructions are available in aligned instruction mode, and only in the first half of a 32-bit instruction word. In general register mode, INWM and SSFUM are also available, and all the available mode-independent instructions that are 16 bits long are padded with sixteen all-zero bits so that they occupy 32 bits instead of 16. The supplementary instruction prefixes are still not available in that mode.
A SETAM mode is also padded with sixteen zero bits in any mode if it is located in a halfword at an even position (that is, one with an address divisible by 4) and it switches to either mode 1001 or mode 1100, the instructions of which are aligned on 32-bit boundaries.
The instruction with opcode 1704nn is the Supervisor Call instruction; it causes what is essentially one of 64 software interrupts, to one of 64 destination addresses whose values are kept in a protected area in a fixed location among the lowest memory addresses.
Switching between modes is handled by the SETAM (Set Addressing Mode) instruction.
Interpreting a single instruction according to a given mode is performed using the INWM (Interpret Next With Mode) instruction, with nn indicating the addressing mode; this instruction is not applicable to modes with a variant alignment. The table below indicates the values of mnn for each mode:
mnn 400: normal mode 404: full opcode mode 406: stack mode 407: register stack mode 410: extended operate mode 411: short shift mode 413: full opcode short memory reference short shift mode 416: condensed mode 417: vector mode 420: extended register short page mode 421: extended register short page stack mode 422: extended register short page extended operate mode 423: extended register short page short shift mode 424: extended short page full opcode mode 425: extended short page short shift full opcode mode 426: extended short page compact mode 427: extended short page compact condensed mode 430: symmetric address mode 434: symmetric vector register mode 440: stateless scratchpad mode 441: register scratchpad mode 444: double base mode 445: flexible register mode 447: simple compact mode 450: stateful scratchpad mode 452: mutable scratchpad mode 454: plain stateful scratchpad mode 456: plain mutable scratchpad mode 460: vector register mode 461: semi-RISC mode 462: alternate mode 463: full opcode alternate mode 464: comprehensive mode 466: universal mode 467: register scratchpad universal mode 470: advanced compound mode 471: modified normal mode 472: stack advanced compound mode 473: large array mode 474: short memory reference mode 475: alternate short memory reference mode 476: mixed operation mode 477: pointer page mode 500: register short page mode 501: register short page stack mode 502: register short page extended operate mode 503: register short page short shift mode 504: short page full opcode mode 505: short page short shift full opcode mode 506: short page compact mode 507: short page compact condensed mode 510: short page mode 511: short page stack mode 512: short page extended operate mode 513: short page short shift mode 514: stateful short page condensed mode 515: mutable short page condensed mode 516: plain stateful short page condensed mode 517: plain mutable short page condensed mode 520: selective register short page mode 521: selective register short page stack mode 522: selective register short page extended operate mode 523: selective register short page short shift mode 524: selective short page full opcode mode 525: selective short page short shift full opcode mode 526: selective short page compact mode 527: selective short page compact condensed mode 530: selective short page mode 531: selective short page stack mode 532: selective short page extended operate mode 533: selective short page short shift mode 534: selective stateful short page condensed mode 535: selective mutable short page condensed mode 536: selective plain stateful short page condensed mode 537: selective plain mutable short page condensed mode 540: aligned instruction mode 546: general register mode 570: three-address RISC mode 574: flexible CISC mode 575: stack machine mode
and then the same codes with 6 replacing 4, and 7 replacing 5, for the direct cache versions of those modes to which direct cache operation is applicable, so that features such as vector operations, supplementary register operations, and extended operations, or the additional data types available in normal mode, are accessible from all modes of operation, without having to switch both to and from another mode. Six bits are allocated to the mode; these instructions can be used to enter the direct cache modes, but not the variant alignment modes.
Switching between operand types used with stateful and mutable scratchpad modes is handled by the SETPT (Set Primary Type) and SETST (Set Secondary Type) instructions, where n indicates the operand type as follows:
000 Byte 001 Halfword 010 Integer 011 Long 100 Medium 101 Floating 110 Double 111 Quad
where the SETST instruction, in addition to setting the secondary type, sets the bit that indicates that a secondary type is in use, and the SETPT instruction, in addition to setting the primary type, will clear that bit if it is setting the primary type to a fixed-point type, but will not change that bit if it is setting the primary type to a floating-point type. This is because memory-reference opcodes allow for 16 basic fixed-point operations, but only 8 basic floating-point operations.
Similarly, switching between operand types used with stack mode and the plain scratchpad modes is done by the SETT (Set Type) instruction.
The SETOTM instruction is used to choose between the eight basic schemes by which six-bit opcodes, as used in some of the addressing modes to be discussed later, are translated into the standard seven-bit opcodes used by memory-reference instructions. (The default translation omits the instructions for the Long, Medium, and Quad data types.)
These instructions set the type associated with the current executing program sequence, and thus may affect one of two different areas of the Program Status Block when bisequential operation is in effect.
Opcodes of the form 17160x and 17161x are used as prefixes to instructions which store data in memory. The last four bits of the instruction indicates the tag value to apply to the word of memory to which the operand is being stored. This applies only in tagged memory mode, which is described in a later section.
The possible tag values, as described in that section, are:
0000 Executable Code 0001 Subsequent Word of Multi-Word Item 0010 Array Descriptor 0011 Character String 0100 Register Packed 0101 Register Packed Long 0110 Simple Floating 0111 Simple Floating Long 1000 Byte 1001 Halfword 1010 Integer 1011 Long 1101 Floating 1110 Double 1111 Quad
The SETPW instruction modifies the way the computer handles data memory, with mn indicating the following:
00: 32-bit word, 8-bit string character 02: 24-bit word, 6-bit string character 03: 36-bit word, 9-bit string character 04: 40-bit word, 10-bit string character 06: 60-bit word, 15-bit string character 12: 24-bit word, 8-bit string character 13: 36-bit word, 6-bit string character 14: 40-bit word, 8-bit string character 16: 60-bit word, 6-bit string character 26: 60-bit word, 10-bit string character
An explanation of how this feature works is contained in the section on the program status block; normally, this feature is only used for emulation purposes.
The SETSW instruction performs the same function for the secondary data formats, and the TSETPW and TSETSW instrucions perform the same operation as the SETPW and SETSW instructions respectively, but also indicate that the change is only intended to be in effect for a few instructions; this will affect how data, stored in the cache in the format associated with the old data memory width changed away from will be treated.
The instruction with opcode 171774 will be the SUSIUM instruction, for Set User Status Immediate Under Mask, and the next 256 bits of the instruction will indicate which bits of the rightmost 256 bits of the program status block are to be changed, and then the subsequent 256 bits of the instruction will be loaded into the corresponding bits of the program status block.
The SSIUM instruction, with opcode 171775, has a 512-bit mask and 512-bit data to address the entire Program Status Block.
The SLSFUM (Set Long Status Field Under Mask) has opcode 173600; the last five bits indicate which group of sixteen bits, from 0 to 31, in the 512-bit program status block is to be modified, and then the opcode is followed by two halfwords, the first being a mask, and the second being the actual values to be placed in those bits of the Program Status Block corresponding to one bits in the mask.
The instruction with opcode 11776, the SSFUM (Set Status Field Under Mask) instruction is a general instruction for setting any portion of the program status block. It is followed by an additional 16 bits, consisting of the following fields:
Thus, this instruction can perform the functions associated with the SETW, SETPT, SETST and SETAM instructions, as well as being useful to enable many other features of the architecture. (Examples are not given here at this time because the format of the Program Status Block has been subject to frequent revisions, and could potentially be subject to further revisions in future.)
Thus, there are four instructions available for making changes to the program status block from within a program; in addition to changing the entire PSO or that portion which may be available to user-mode programs, either sixteen bits or four bits can be dealt with at a time. The organization of the Program Status Block makes these particular divisions useful for many purposes.
The REP instruction is similar to the repeat instructions found on the Univac 1103 computer and the Strela from the Soviet Union.
A 16-bit field indicates the number of times the subsequent instruction is to be repeated; the last three bits of the instruction increment the source, operand (if applicable) and destination addresses.
This increment is internal, and does not require the instruction to be indexed, or alter the contents of the index registers or other registers.
The increment is always in terms of the full size of the operand.
Register addresses may be incremented. If used with a long vector instruction, an increment always proceeds past 64 elements of the operand type, and it can also proceed from one long vector register to the next, or one long vector scratchpad register to the next (each of which consists of 64 scalar registers).
One of the significant benefits of this instruction is that it allows any pipelining features present in an implementation to be used with any instruction in order to vectorize it. Thus, a requirement for this instruction to function correctly is that each of the iterations of the repetition is logically independent; source and destination vectors must not overlap, for example.
As it may be possible to overlap more than one instruction in fully-pipelined vectorized mode, the CPS (Compose Pipeline Sequence) instruction is also provided.
After the first halfword with the opcode, the next one contains the count of the number of repetitions to be performed. Then, there are a series of three-bit fields, indicating if the destination, operand, and/or source addresses of each of the instructions in the sequence are to be incremented on each iteration, as with the REP instruction. These are contained in a series of halfwords which begin with zero, and which each contain five such fields, if required, and finally one halfword beginning with a one, containing four such fields, and a three-bit field indicating how many, from zero to four, of them are used. Then, the instruction is followed by as many instructions to include in the pipeline sequence as are indicated by the number of these fields which are present and indicated as being used.
A normal loop construct would be sufficient to cause consecutive instructions in a program to overlap in the pipeline, so that, as long as issues such as logical dependencies do not prevent it, one instruction is issued per cycle. This special instruction is intended to allow an even denser usage of the computer's arithmetic-logic units to be specified.
Each instruction within a pipeline sequence defined with a CPS instruction is to be issued once per cycle, following the first time it is issued.
This means that all the instructions in that sequence may reach their execute phases simultaneously, although for different iterations of the sequence.
Therefore, no two instructions in a sequence formed with a CPS instruction can use the same portion of the same ALU, where the portions into which an ALU is divided are:
thus, the CPS instruction can only be used to compose fairly simple vector operations, such as a multiply-and-accumulate. However, an operation on a floating-point vector and one on a similar fixed-point vector can be interleaved, and extended operate instructions can also be included in a sequence (one only of each type).
Short vector instructions can be included in a sequence, but the short vector ALU is not divided into parts.
Simple floating multiplication and division instructions also use the addition portion of the integer ALU in addition to the multiplication or division portion.
Normally, long vector instructions cannot be part of the sequence composed by a CPS instruction, as they are usually performed by pipelining the operations on the consecutive elements of a vector in a single ALU. However, in the case of a high-performance implementation of the architecture, which provides a set of sixty-four arithmetic-logic units to handle all the elements of a long vector in parallel, and which therefore may also provide the cache-internal parallel computing feature, the CPS instruction can be applied to such instructions, allowing the maximum possible performance to be obtained from the computer. Multi-way long vector instructions are always treated as using all portions of the ALU used for the data type.
There can be no logical dependencies between instructions in one iteration of a CPS sequence and a subsequent iteration, and subsequent iterations cannot use the same resources in any way that can lead to interference as these iterations execute concurrently with a delay of only one cycle between them. One consequence of these restrictions is that operands whose location is not incremented can only be used as constants, never as working registers or working storage. Values can be stored in register or memory operands whose location is incremented, on the assumption that they will not be read back in during the execution of the complete CPS sequence; if this assumption is not true, the values read back in will be unpredictable.
The first occurrence of a given instruction in a CPS sequence, however, may be delayed by more than one cycle from the first occurrence of the immediately preceding instruction. Thus, subject to the restriction above on the use of resources, logical dependencies are permitted between one instruction and subsequent instructions in the same iteration of the sequence.
One way subsequent instructions in the same CPS sequence can work on the same data without having subsequent iterations use the same resources would be to store the intermediate results in vectors in memory. To avoid forcing the unnecessary use of memory for intermediate results, when register 0 of any group of registers (including the vector registers and the vector scratchpad) is a non-incremented operand of an instruction, the actual register 0 is not used, and instead this references an intermediate result passed from one instruction to the next in the pipeline. Thus, storage of values in register 0 as a non-incremented operand is allowed.
Again, because the next repetition of the group of instructions forming the pipeline sequence is intended to begin before the previous repetition has ended, actual registers cannot be used for intermediate results. While the actual register 0 could only contain one value at a time, iterations proceeding concurrently in different stages would be, at any given time, using a register address of 0 to stand for different and independent portions of the arithmetic unit.
One important limitation of the use of register 0 in this fashion is that a value stored in temporary storage using register address 0 can only be read back in by the immediately following instruction in a given iteration of a pipeline sequence.
Note that when determining the number of instructions that are affected by a CPS instruction, the INUAF, INWM, and the supplementary instruction prefix are not counted as separate instructions, but as part of the instruction that follows them.
Also, string and packed decimal instructions cannot be used with REP or CPS, but register packed instructions can be.
The FLL instruction is similar in form to the CPS instruction, but does not have any of its restrictions. The additional field consisting of the least significant three bits in the first sixteen bits of the instruction, if they are nonzero, indicates which of the arithmetic/index registers, when its contents are read by an instruction inside the loop, will instead stand for the loop counter, which will start with 0 and increase by 1 for each iteration of the loop. If that field contains zero, the loop counter will not be accessible within the loop. The FLL instruction may contain any other instruction, and may even be nested. Its purpose is to make it simple for the instruction issuer to produce the same sequence of micro-operations for a loop as it would produce if the loop had been unrolled, without the need to fetch additional instructions or consume memory storing them. Note that if all loop counters must be accessible, the FLL instruction would not be able to be nested more than seven deep.
A limit to nesting FLL instructions, however, is clearly required, to allow the complexity of the instruction issuer to be bounded. Allowing a maximum of sixteen levels of nesting appears to be sufficiently generous. Note that interrupts can occur after the individual instructions under the control of an FLL instruction; when this happens, side information is contained in the model-dependent portion of the machine state. The issuing of micro-operations called for by FLL sequences can be terminated by flushing the thread to which they belong from execution.
The RMOI instruction modifies normal instructions, and vector instructions as used in the vector register mode, so that their arguments contain multiple operands.
Instructions involving a floating-point destination register of any kind, including the various floating-point vector registers, when modified with the RMOI prefix, always take a 128-bit argument; this argument may contain a pair of 64-bit double precision floating point numbers if a double-precision instruction is modified, four 32-bit single precision floating point numbers if a single-precision instruction is modified, and eight 16-bit short floating point numbers, as used with the short vector instructions, if a medium precision instruction is modified.
Instructions involving one of the arithmetic/index registers as their destination register, when modified with the RMOI prefix, take a 32-bit argument; those using one of the fixed-point supplementary registers as their destination register (or the entire group of fixed-point supplementary registers as the fixed-point vector accumulator, or a fixed-point vector register or a location in the fixed-point vector scratchpad) take a 64-bit argument. The type of the instruction being modified determines whether the argument is divided into four or eight 8-bit bytes, two or four 16-bit halfwords, or, in the case of 64-bit arguments only, two 32-bit words.
It is expected that implementations will, when the RMOI prefix is used, start the arithmetic operations on the successive components of the operands on successive clock cycles; the primary benefit of the RMOI prefix is simply to conserve register space, and provide an additional means of performing operations compatible with short vector operations. Additional speed will still be obtained by permitting more operations to be specified as pipelined at one time; also, in the trivial case of fixed-point addition and subtraction, partitioning the arithmetic units may only require minimal additional circuitry, and thus the operations may be performed in parallel in this case. As with short vector floating-point operations, the values stored in registers between operations will not contain any guard bits.
The SPC, SPCAN, and SPCIB instructions are used with the Bisequential Operation feature of the computer, particularly when the computer is in suspended bisequential mode. In this mode, programs can switch between using one of two different program counters to fetch the next instruction. This lets two processes which are closely interlocked run with arbitrary concurrency with low overhead. The SPC instruction immediately toggles which program counter is being used; the SPCAN instruction causes the toggle to take place after the next instruction, which could be a jump instruction (note that when this mode is enabled, changeover to the auxilliary program counter must first be done in association with a jump instruction to initialize that program counter); and the SPCIB instruction is used preceding a conditional branch instruction, and causes a change in the program counter used only if the branch is taken. Used with a non-branch instruction, it has no effect; used with an unconditional branch, it toggles the program counter.
The INUAF instruction is used to facilitate conversion from one data format to another; the instruction it precedes uses the integer and floating-point formats, and the data width, and the endian conventions, indicated by the bits in the Program Status Block giving secondary formats. Note that as the format of the internal contents of floating-point registers may depend on the floating-point format in use, conversions from the alternate format in memory and the current standard format in the registers accompany any instruction so prefixed where necessary.
Note that if operand filtering, as described in the section on code 12 microprograms, is in effect, it is in effect only for the normal format, not the secondary format.
When the computer is in suspended dual-format mode, the SNF and SSF instructions are also available to switch between using the normal format and the secondary format.
The FCBPT and FCBPNT instructions act as no-operation instructions as far as the action to be performed by a program is concerned, but their purpose, when placed before a conditional-branch instruction, is to indicate whether that conditional branch instruction will be taken in most cases (as for the instruction that repeats a loop) or will not be taken in most cases. This allows the efficiency of branch prediction to be improved.
The instruction with opcode 1737nn has the effect of causing the bits in nn to be treated as bits which supplement the opcode portion of the instruction. Therefore, this instruction effectively acts as the first 16 bits of an instruction belonging to a greatly-expanded repertoire.
The instructions have the same addressing mode, and usually have the same format, as the one currently in effect for normal instructions. In one case, prefixed instructions with a given opcode have the format of the corresponding instruction with a different opcode; this is done to allow more instructions analogous to packed decimal instructions to be provided for the prefix which provides additional data types. Where the opcodes for the instructions are shown, they are shown as they would appear in normal mode.
The six principal types of prefixed instructions, involving the prefixes 173701, 173702, 173703, 173704, 173705, and 173706 will be described in subsequent sections. (The prefix 173700 is reserved for the case where an instruction prefix is composed of more than one halfword, adding a further 65,536 possible instruction prefixes to a basic set of 63 instruction prefixes.)
The opcodes 173730 of this type prefix instructions that are indicated as operating on program memory rather than data memory; this distinction is used when the computer is operating in 24-bit word or 36-bit word mode (or 40-bit word mode, or 30-bit word mode) for emulation purposes, so that when in these modes it is still possible to use techniques such as just-in-time compilation. (Just-in-time compilation using Code 12 microprograms, however, does not require a prefix of this type, since the operands of the extended operate instruction associated with these microprograms are already designated as belonging to the appropriate type of memory.) Note that this prefix may be applied to a prefixed instruction.
The opcodes 17376n of this type is used as the prefix for instructions to modify the Memory Map ID and create child processes, which are available to ring 0 processes which may be otherwise unprivileged.
The opcodes 17377n of this type act as the prefix to instructions that are only available in supervisor mode, such as I/O instructions, instructions to return from an interrupt, the processor halt instruction, and so on.
The instructions of this type will be discussed in a later section, once the Program Status Block and the overall architecture of the machine have been dealt with.
As noted above, both the short vector instructions and the extended translate instructions will be described in their own sections.