The formats of the remaining operate instructions are shown below:
and their opcodes are as follows:
1500xx SLBR Supplementary Load Base Register 1510xx SSTBR Supplementary Store Base Register 1505xx SLSB Supplementary Load Scratchpad Base 1515xx SSSB Supplementary Store Scratchpad Base 1506xx SLPSB Supplementary Load Pointer Scratchpad Base 1516xx SSPSB Supplementary Store Pointer Scratchpad Base 1507xx SLASB Supplementary Load Array Scratchpad Base 1517xx SSASB Supplementary Store Array Scratchpad Base 152xxx LMU Load Multiple 153xxx STMU Store Multiple 154xxx LMUBR Load Multiple Base Registers 155xxx STMUBR Store Multiple Base Registers 156xxx LMUQ Load Multiple Quad 157xxx STMUQ Store Multiple Quad 1601xx BL Branch if Low 1602xx BE Branch if Equal 1603xx BLE Branch if Low or Equal 1604xx BH Branch if High 1605xx BNE Branch if Not Equal 1606xx BHE Branch if High or Equal 1607xx BNV Branch if No Overflow 1610xx BV Branch if Overflow 1612xx BC Branch if Carry 1613xx BNC Branch if No Carry 1617xx BRA Branch 163xxx JMS Jump to Subroutine 163xx0 BRS Branch to Subroutine 1641xx JL Jump if Low 1642xx JE Jump if Equal 1643xx JLE Jump if Low or Equal 1644xx JH Jump if High 1645xx JNE Jump if Not Equal 1646xx JHE Jump if High or Equal 1647xx JNV Jump if No Overflow 1650xx JV Jump if Overflow 1652xx JC Jump if Carry 1653xx JNC Jump if No Carry 1657xx JMP Jump 1641x0 LBL Long Branch if Low 1642x0 LBE Long Branch if Equal 1643x0 LBLE Long Branch if Low or Equal 1644x0 LBH Long Branch if High 1645x0 LBNE Long Branch if Not Equal 1646x0 LBHE Long Branch if High or Equal 1647x0 LBNV Long Branch if No Overflow 1650x0 LBV Long Branch if Overflow 1652x0 LBC Long Branch if Carry 1653x0 LBNC Long Branch if No Carry 1657x0 LBRA Long Branch 166xxx JXH Jump if Index High 167xxx JXLE Jump if Index Low or Equal 166xx0 LBXH Long Branch if Index High 167xx0 LBXLE Long Branch if Index Low or Equal 164100 RL Return if Low 164200 RE Return if Equal 164300 RLE Return if Low or Equal 164400 RH Return if High 164500 RNE Return if Not Equal 164600 RHE Return if High or Equal 164700 RNV Return if No Overflow 165000 RV Return if Overflow 165200 RC Return if Carry 165300 RNC Return if No Carry 165700 RSS Return from Stack Subroutine 17000x 0000xx SHLB Shift Left Byte 17001x 0000xx SHRB Shift Right Byte 17003x 0000xx ASRB Arithmetic Shift Right Byte 17004x 0000xx ROLB Rotate Left Byte 17005x 0000xx RORB Rotate Right Byte 17006x 0000xx RLCB Rotate Left through Carry Byte 17007x 0000xx RRCB Rotate Right through Carry Byte 17100x 0000xx SHLH Shift Left Halfword 17101x 0000xx SHRH Shift Right Halfword 17103x 0000xx ASRH Arithmetic Shift Right Halfword 17104x 0000xx ROLH Rotate Left Halfword 17105x 0000xx RORH Rotate Right Halfword 17106x 0000xx RLCH Rotate Left through Carry Halfword 17107x 0000xx RRCH Rotate Right through Carry Halfword 17200x 0000xx SHL Shift Left 17201x 0000xx SHR Shift Right 17203x 0000xx ASR Arithmetic Shift Right 17204x 0000xx ROL Rotate Left 17205x 0000xx ROR Rotate Right 17206x 0000xx RLC Rotate Left through Carry 17207x 0000xx RRC Rotate Right through Carry 17300x 0000xx SHLL Shift Left Long 17301x 0000xx SHRL Shift Right Long 17303x 0000xx ASRL Arithmetic Shift Right Long 17304x 0000xx ROLL Rotate Left Long 17305x 0000xx RORL Rotate Right Long 17306x 0000xx RLCL Rotate Left through Carry Long 17307x 0000xx RRCL Rotate Right through Carry Long
The ordinary instructions in this group will be described in this section, and the mode-independent instructions will be described in a later section.
The LM and STM instructions operate on a range of destination registers specified in the instruction, and are useful for saving and restoring registers when a subroutine is called. The LMBR and STMBR instructions, and the LMQ and STMQ instructions perform the same function for the base registers and the floating-point registers.
The various supplementary load and store instructions provide memory-reference instructions which only have the simple register-memory addressing mode, to allow access to individual base and scratchpad registers.
If the base register zero is indicated in these instructions, the address field is omitted. Unlike the case of standard memory-reference instructions, base register zero is used, however: in the case of a store instruction, it serves as a pointer to the memory to which information is stored, and the length of the information stored is then added to its contents; in the case of a load instruction, the length of the information to be read is first subtracted from its contents, and then it is used as a pointer to that information.
In other words, the load and store multiple instructions, when base register zero is indicated, are POP and PUSH instructions, with base register zero serving as a stack pointer. This also applies to the multiple-register short vector instructions.
Note that these instructions will execute successfully even when they are performing unaligned reading or writing of data. Also note that only the complete contents of a register may be placed on a stack or removed from it; there are no byte, halfword, floating or double PUSH or POP instructions.
These are the instructions which carry out a transfer of control, causing the steps of the program being executed to be fetched from an address different from the next one in sequence. Some of these instructions involve bits of the status word. There is a carry bit which is set, either to 0 or to 1, by operations that could produce a carry out of one of the 32-bit arithmetic/index registers. Also, other bits indicate if the result of an arithmetic operation, whether integer or floating-point, is positive, negative, or zero. These determine if a conditional jump instruction results in a jump.
If the base register field in a JMP or conditional jump instruction is zero, the address field of the instruction, instead of being treated as an unsigned and therefore positive number of bytes, is treated as a signed number of halfwords, relative to the value the program counter would normally have when fetching the next instruction; thus, a value of 0 indicates the next instruction in sequence. This provides the various long branch instructions. As well, another modified form of the conditional jump instructions, but not the loop instructions or the subroutine jump instruction, is available with a six-bit displacement, also in halfwords; these have opcodes of the form 160xxx instead of 164xxx.
Also, the rR field in a JMS instruction refers to a base register rather than an arithmetic/index register. Thus, to return from a subroutine called by a JMS instruction, a jump instruction using the same base register and with an address field containing zero is used. (Note that a nonzero address field can be used if space following the JMS instruction is to be skipped because it is used to pass information, such as a pointer to an argument list, to the subroutine, following some manner of calling convention. Usually, however, the pointer to the argument list will be put in a register designated by convention for this purpose, such as base register 1.)
If the rR field is zero, however, instead of the return address being stored in base register zero, it is stored in the memory location pointed to by base register zero, which is then incremented by either 4 or 8. This allows the use of base register zero as a stack pointer, and the use of that stack for subroutine jumps.
Also note that the use of a base register for storing the return address of a JMS instruction or an LBRS instruction allows a LBRS to the next instruction in sequence to be used for the purpose of initializing a base register to point to the current sequence of executing code.
Thus, if the base register field in a JMP or conditional jump instruction is zero, and the jX field is zero as well, the instruction then pops the new program counter value from the stack. This provides the Return from Stack Subroutine instruction and the conditional return instructions.
The JV instruction transfers control if an overflow condition is present; the other conditional jumps never transfer control if an overflow is present.
If indexed addressing is used in a jump instruction, the instruction does not jump to the memory location at the effective address, but instead to the location whose address it contains. This addressing mode, post-indexed indirect addressing, allows branching to one of several locations in a list. This also applies to the JMS instruction.
The JXH and JXLH instructions decrement and increment, respectively, the count register specified in the cR field, compare it to the limit register specified in the lR field, and jump if the count register is high in the first case, or low or equal in the second.
A number of very basic operations, other than the shift instruction, which apply to a single operand are useful to have in a computer, such as complementing a value or clearing it to zero.
Several such operations are defined:
17220x CLR Clear 17320x CLRL Clear Long 17221x ABS Absolute Value 17321x ABSL Absolute Value Long 17222x INV Invert 17322x INVL Invert Long 17223x NEG Negate 17323x NEGL Negate Long
The Clear instruction sets a register to zero; the Invert instruction inverts all the bits; the Negate instruction produces the two's complement of the register's contents, producing no change in the register's value, and an overflow condition, if the register has its first bit set and all remaining bits zero. The Absolute Value instruction performs a Negate operation only if the register contents are negative.
The instructions
1701xx NB Normalize Byte 1711xx NH Normalize Halfword 1721xx N Normalize 1731xx NL Normalize Long
shift the contents of the source register left as many times as necessary to make the first bit of the source operand a 1, and store the number of required shifts in the destination register. The type of the instruction applies to the source operand: the destination always is a full 32-bit register.
As the instruction set described here is quite an elaborate one, designed to accelerate computations as much as possible, it is not unreasonable to include, as some existing architectures have already included, instructions to calculate various mathematical functions in hardware.
17440x SINM 17540x SIN 17640x SIND 17740x SINQ
17441x COSM 17541x COS 17641x COSD 17741x COSQ
17442x TANM 17542x TAN 17642x TAND 17742x TANQ
17444x ASNM 17544x ASN 17644x ASND 17744x ASNQ
17445x ACSM 17545x ACS 17645x ACSD 17745x ACSQ
17446x ATNM 17546x ATN 17646x ATND 17746x ATNQ
17450x SINHM 17550x SINH 17650x SINHD 17750x SINHQ
17451x COSHM 17551x COSH 17651x COSHD 17751x COSHQ
17452x TANHM 17552x TANH 17652x TANHD 17752x TANHQ
17454x ASNHM 17554x ASNH 17654x ASNHD 17754x ASNHQ
17455x ACSHM 17555x ACSH 17655x ACSHD 17755x ACSHQ
17456x ATNHM 17556x ATNH 17656x ATNHD 17756x ATNHQ
17460x SQRM 17560x SQR 17660x SQRD 17760x SQRQ
17461x QBRM 17561x QBR 17661x QBRD 17761x QBRQ
17462x LOGM 17562x LOG 17662x LOGD 17762x LOGQ
17463x EXPM 17563x EXP 17663x EXPD 17763x EXPQ
17764x CLRQ
17765x ABSQ
17766x SGNQ
17767x NEGQ
The LOG and EXP instructions operate to the base two; the hyperbolic functions are similarly scaled; the trignometric functions take their arguments in circles where one circle equals 360 degrees or two times pi radians, and the accuracy of the sine is limited for small arguments; the functions may be implemented by means of the CORDIC algorithm or related algorithms.
The SGNQ instruction produces 0 if its argument is zero, and +1 for a positive argument and -1 for a negative argument.
The Extensible Shift instructions perform what is termed a "funnel shift", to facilitate shifting of multi-word operands of arbitrary length. The two instructions are:
1741xx ESL Extensible Shift Left 1751xx ESR Extensible Shift Right
The source argument consists of one arithmetic/index register, and the destination argument consists of two consecutive arithmetic/index registers, and is not restricted to starting with an even-numbered register.
In an Extensible Shift Left instruction, the source argument value is considered to initially occupy the rightmost portion of a space the size of the destination argument prior to being shifted left.
Similarly, in an Extensible Shift Right instruction, the source argument value is considered to initially occupy the leftmost portion of a space the size of the destination argument prior to being shifted right.
Note that it is always possible to perform the operation of one of these instructions with the other one, as only those shifts are valid which result in the source operand remaining entirely within the double-width field. However, both are retained for lower-performance implementations in which a shift operation may take a time proportional to the number of shifts specified.
Once the source argument value is prepared, then the destination is altered as follows:
Bits in the destination argument which do not correspond to bits from the original source argument are unchanged.
Bits in the destination argument which do correspond to a bit from the original source argument are replaced by one of the four bits in the four-bit connective field in the instruction, where these bits correspond, in order, to the possible combinations of a value for the source bit and the destination bit as follows:
Source bit: 0 0 1 1 Destination bit: 0 1 0 1
Thus, if the connective field contains 0111, those bits are replaced by the OR of the source bit and the destination bit; if the connective field contains 0011, the bits in the destination operand that correspond to bits in the original source operand are simply replaced by those bits. Note that a field of this type was used on the AN/FSQ-32 computer, but for general logical operations instead of only for this particular specialized logical operation.