The IBM 704 computer was one of the earlier computers which, while it used vacuum tubes for its logic circuits, used core memory rather than either a magnetic drum or some type of delay line for its main memory. This gave it the programming convenience of random-access memory without the reliability and pattern-sensitivity problems of Williams tubes, making it understandable to users of modern computers.
It had a number of successors which added new features, but retained compatibility. There was the IBM 709, also a vacuum-tube machine, and the transistorized IBM 7090 and 7094, as well as the less expensive and smaller-scale IBM 7040 and 7044.
This family of computers was very popular and successful for IBM. From 1954 to 1964, it was the best known family of large scientific computers.
There are a few things about this architecture which might seem strange to people used to today's computers.
The manual for the DDP-24 computer, in an appendix, noted that sign-magnitude representation, which it also used, was the best choice; one's complement was used on most computers, and two's complement was used on less-expensive models! The prestige of IBM's 704 and its successors may have helped encourage such thinking. While it is true that sign-magnitude format is the most similar to the way people write numbers down, a complete turn-around in thinking later took place leading to people seeing no rational reason to bother with the complexities of any fixed-point format other than two's complement, which has the advantage of easily permitting unsigned arithmetic as well. The IBM 360, which used two's complement notation for integers, may have helped to bring about this change of thinking.
The IBM 704 computer, which was similar in price to the IBM 701, but considerably more powerful, was a very successful machine for IBM, which established it as a major computer company.
The IBM 709 computer added a considerable number of new instructions to the architecture, including powerful features like the convert instructions.
The IBM 7090 computer was largely a transistorized implementation of the IBM 709. While it did not add new computational instructions to the architecture, there was an important modification to how input/output was done. The IBM 7090 could use channels, auxilliary processors which allowed input or output of data to or from memory without involving the CPU. As well, the cycle time of the IBM 7090 was five times faster than that of the IBM 709. One feature was dropped, the ability to use drum memory as a supplement to core memory.
The IBM 7094 computer added two important features to the architecture; hardware double-precision floating point, and the ability to use seven index registers rather than three. A faster version, the IBM 7094 II, was also available; in addition to using faster memory, it included an enhanced, but still limited, pipelining capability over that of the regular 7094.
The IBM 7040 and 7044 were a family of two computers, the 7044 being faster, which retained the ability to perform double-precision floating-point in hardware, introduced with the 7094, and which added some new features of its own, such as instructions that handled individual 6-bit characters in a 36-bit word, but which had a streamlined instruction set, omitting many instructions present in other machines. Some of the instructions omitted were little-used, but useful features, such as the convert instructions introduced with the 709, or the ability to use seven index registers, introduced with the 7094, were also left out.
Each instruction occupied a 36-bit word. The instruction formats are shown below:
Originally, the instructions were all described as belonging to either Type A or Type B.
The second instruction format, termed type B, was the more usual one for single-address instructions. The first format, type A, was used for a few special instructions for operations such as looping.
The Type B instructions were later divided into several groups, at least in one textbook of IBM 7090 programming (Programming the IBM 7090: A Self-Instructional Programmed Manual, James A. Saxon, Prentice-Hall). The last of these groups, the Type E instructions, were present originally in the IBM 704 computer. One modification made in the IBM 709 and later machines was the addition of indirect addressing, which could be indicated by setting both of the flag bits equal to 1.
The IBM 7094 included another modification; originally, each bit in the index register field indicated that one of three index registers were used; if more than one was set, the result of an OR between the selected registers was used. (In the case of some instructions, this caused the result of the OR to replace the contents of the registers, which was not clearly noted in the descriptions of those instructions in the manuals for later machines with this architecture!) In the IBM 7094, there were instead seven index registers, one of which could be selected with each nonzero value in this field, although a compatible mode of operation using only three index registers could also be selected.
The field specifying an index register was called the Tag field. When its contents were zero, it indicated an instruction was not indexed. Instructions which used that field to indicate that an index register was the source of an operand would have the constant zero as their operand if this field contained zero.
The IBM 7040 and 7044 computers, while they had double-precision floating-point instructions like the 7094, and also had a memory protection feature which no previous model had, did not have the option of seven index registers.
Type C instructions were variable length instructions. Since a count field of 6 bits was only needed because the 36 bits in a word exceeded 31, the largest number a 5-bit field could represent, a count of 48 or greater would not normally be used, and thus extra circuitry was not included to prevent the first two bits in that area from still triggering indirect addressing.
The IBM 7040 and 7044 computers had instructions that referred to one of six characters in a word; this character was indicated by part of the count field, and the two unused values were used to indicate other instructions. These and other instructons began with the three bits 101 instead of 000 as did all non-type A instructions on the earlier machines. This addition to the possible instruction formats is shown in the bottom four lines of the diagram.
The Type A instructions were:
TXI 001 +1000 Transfer with Index Incremented TIX 010 +2000 Transfer on Index TXH 011 +3000 Transfer on Index High STR 101 -1000 Store Location and Trap  * TNX 110 -2000 Transfer on No Index TXL 111 -3000 Transfer on Index Low or Equal
The third column shows how the opcodes were conventionally noted, although the next three octal digits did not need to be zero. The STR instruction was present on the 7040 and 7044, but to make additional opcodes available, on those machines a 12-bit opcode rather than a 3-bit opcode was required.
These instructions took the following actions:
Transfer with Index Incremented: Add the decrement to the indicated index register, and jump to the location indicated by the address.
Transfer on Index: If subtracting the decrement from the index register would produce a positive result, perform the subtraction and branch to the location indicated by the address. If the result would be negative or zero, do not modify the index register, and do not branch.
Store Location and Trap: This instruction stored a return address in memory location zero, and caused a branch to memory location 2. It was essentially a software interrupt instruction, and was a later addition to the architecture, not being present on the 704.
Transfer on Index High: If the contents of the index register are greater than the value in the decrement field, jump to the location indicated in the address field.
Transfer on No Index: If subtracting the decrement from the index register would produce a positive result, perform the subtraction but do not branch. If the result would be negative or zero, do not modify the index register, but branch to the location indicated by the address.
Transfer on Index Low or Equal: If the contents of the index register are less than or equal to the value in the decrement field, jump to the location indicated in the address field.
The Type B instructions, excluding input-output instructions, were:
HTR +0000 Halt and Transfer * TRA +0020 Transfer TTR +0021 Trap Transfer * ESNT -0021 Enter Storage Nullification Mode and Transfer  * TLQ +0040 Transfer on Low MQ * IIA +0041 Invert Indicators from AC  * TIO +0042 Transfer if Indicators On  * RIA -0042 Reset Indicators from AC  * OAI +0043 OR Accumulator to Indicators  * PAI +0044 Place Accumulator in Indicators  * TIF +0046 Transfer if Indicators Off  * PIA -0046 Place Indicators in Accumulator  * IIR +0051 Invert Indicators of Right Half  * IIL -0051 Invert Indicators of Left Half  * RFT +0054 Right Half Indicators, Off Test  * LFT -0054 Left Half Indicators, Off Test  * SIR +0055 Set Indicator of Right Half  * SIL -0055 Set Indicator of Left Half  * RNT +0056 Right Half Indicators, On Test  * LNT -0056 Left Half Indicators, On Test  * RIR +0057 Reset Indicators of Right Half  * RIL -0057 Reset Indicators of Left Half  * TSX +0074 Transfer and Set Index TZE +0100 Transfer on Zero TNZ -0100 Transfer on No Zero CVR +0114 Convert by Replacement from AC  * CAQ -0114 Convert by Addition from MQ  * TPL +0120 Transfer on Plus TMI -0120 Transfer on Minus XCL -0130 Exchange Logical Accumulator and MQ  * XCA +0131 Exchange Accumulator and MQ  * TOV +0140 Transfer on Overflow TNO -0140 Transfer on No Overflow * CRQ -0154 Convert by Replacement from MQ  * TQO +0161 Transfer on MQ Overflow * TQP +0162 Transfer on MQ Plus * MPY +0200 Multiply MPR -0200 Multiply and Round * VLM +0204 Variable Length Multiply  DVH +0220 Divide or Halt * DVP +0221 Divide or Proceed VDH +0224 Variable Length Divide or Halt  * VDP +0225 Variable Length Divide or Proceed  FDH +0240 Floating Divide or Halt * DFDH -0240 Double-Precision Floating Divide or Halt  * FDP +0241 Floating Divide or Proceed DFDP -0241 Double-Precision Floating Divide or Proceed  FMP +0260 Floating Multiply UFM -0260 Unnormalized Floating Multiply DFMP +0261 Double-Precision FP Multiply  DUFM -0261 Double-Precision Unnormalized FP Multiply  * FAD +0300 Floating Add UFA -0300 Unnormalized Floating Add DFAD +0301 Double-Precision FP Add  DUFA -0301 Double-Precision Unnormalized FP Add  * FSB +0302 Floating Subtract UFS -0302 Unnormalized Floating Subtract FAM +0304 Floating Add Magnitude  * UAM -0304 Unnormalized Add Magnitude  * DFAM +0305 Double-Precision FP Add Magnitude  * DUAM -0305 Double-Precision Unnormalized FP Add Magnitude  * FSM +0306 Floating Subtract Magnitude  * USM -0306 Unnormalized Subtract Magnitude  * DFSM +0307 Double-Precision FP Subtract Magnitude  * DUSM -0307 Double-Precision Unnormalized FP Subtract Magnitude  ANS +0320 AND to Storage * ANA -0320 AND to Accumulator ERA +0322 Exclusive OR to Accumulator  * CAS +0340 Compare Addumulator with Storage LAS -0340 Logical Compare AC with Storage  ACL +0361 Add and Carry Logical Word ADD +0400 Add SBM -0400 Subtract Magnitude * ADM +0401 Add Magnitude * SUB +0402 Subtract HPR +0420 Halt and Proceed * IIS +0440 Invert Indicators from Storage  * LDI +0441 Load Indicators  * OSI +0442 OR Storage to Indicators  * DLD +0443 Double Load  * OFT +0444 Off Test for Indicators  * RIS +0445 Reset Indicators from Storage  * ONT +0446 On Test for Indicators  * CLA +0500 Clear and Add CAL -0500 Clear and Add Logical Word ORA -0501 OR to Accumulator CLS +0502 Clear and Subtract ZET +0520 Storage Zero Test  * NZT -0520 Storage Not-Zero Test  * XEC +0522 Execute  LXA +0534 Load Index from Address LXD -0534 Load Index from Decrement LAC +0535 Load Complement of Address in XR  LDC -0535 Load Complement of Decrement in XR  LDQ +0560 Load MQ ENB +0564 Enable  * STZ +0600 Store Zero  STQ -0600 Store MQ STO +0601 Store SLW +0602 Store Logical Word ORS -0602 OR to Storage DST -0603 Double Store  * STI +0604 Store Indicators  * SLQ -0620 Store Left Half MQ * STA +0621 Store Address STD +0622 Store Decrement STT +0625 Store Tag  * STL =0625 Store Instruction Location Counter  STP +0630 Store Prefix * SXA +0634 Store Index in Address  SXD -0634 Store Index in Decrement SCA +0636 Store Complement of Index in Address  * SCD -0636 Store Complement of Index in Decrement  * CPY +0700 Copy and Skip * PAX +0734 Place Address in Index PDX -0734 Place Decrement in Index PAC +0737 Place Complement of Address in XR  PDC -0737 Place Complement of Decrement in XR  PXA +0754 Place Index in Address  PXD -0754 Place Index in Decrement PCA +0756 Place Complement of Index in Address  * PCD -0756 Place Complement of Index in Decrement  * NOP +0761 No Operation * LLS +0763 Long Left Shift LGL -0763 Logical Left LRS +0765 Long Right Shift LGR -0765 Logical Right Shift  ALS +0767 Accumulator Left Shift ARS +0771 Accumulator Right Shift RQL -0773 Rotate MQ Left AXT +0774 Address to Index True  AXC -0774 Address to Index Complemented  *
Asterisks mark the large number of instructions which were omitted on the 7040 and 7044.
The CLA (Clear and Add) instruction is what one would normally think of as a load instruction; in addition to showing how it was implemented, this name reminds us that the instruction sets condition codes.
ADM (Add Magnitude) adds the absolute value of the memory operand to the contents of the accumulator, placing the result in the accumulator.
MPY (Multiply) multiplies the contents of the Multiplier Quotient register by the memory operand; the most significant half of the product is placed in the Accumulator, the least significant half in the Multiplier Quotient register. The MPR (Multiply and Round) instruction increments the magnitude portion of the accumulator after the multiplication if the most significant bit of the magnitude portion of the MQ is a one; this is useful if the numbers being multiplied are considered to be fractions instead of integers.
RND (Round) increments the magnitude part of the Accumulator if the most significant bit of the magnitude part of the Multiplier Quotient register is a 1. This can be used to produce single-precision results of multiplying 36-bit fractions.
Division treats the Accumulator followed by the Multiplier Quotient register (skipping its sign) as a double-length integer, divides by the memory operand, placing the quotient in the Multiplier Quotient register and the remainder in the Accumulator. The DVP (Divide and Proceed) instruction sets a flag if there is an error; the DVH (Divide or Halt) instruction would also halt the computer.
The STP (Store Prefix) instruction modified the first three bits of a memory operand, leaving the rest unchanged; STA (Store Adddress) and STD (Store Decrement) modified the parts of a memory word corresponding to those fields of an instruction. These instructions aided in the use of self-modifying code.
The SLW (Store Logical Word) instruction stored the intermediate P carry bit instead of the sign bit in the sign position of the memory location in which the accumulator contents were stored. This facilitated unsigned arithmetic, for which CAL (Clear and Add Logical Word) and ACL (Add and Carry Logical Word) were also required.
The accumulator of the IBM 704 and its successors was structured as having first the S or sign bit, then the Q bit, a secondary carry bit, then the P bit, which could be a carry bit, or the first bit of the 36-bit accumulator for unsigned arithmetic, and finally the 35 bits of the magnitude portion of the accumulator.
Shift instructions used the last eight bits of the address field for the shift count. Normally, shifts included the Q and P bits, but did not include the sign bit. Long shifts also included the 35 magnitude bits of the MQ register.
Logical operations, such as AND or ORA, involved the P bit and not the S bit.
The FAD, FSB, UFA, and UFS instructions produce a double-precision sum, with the most significant part in the Accumulator and the least significant part in the MQ.
The FMP instruction produced a double-precision product, its least significant part being placed in the MQ.
The FDH and FDP instructions placed their quotient in the MQ. A remainder, based on considering the division as an integer division applied to the mantissas of the numbers involved, was placed in the accumulator.
The HTR (Halt and Transfer) instruction modified the program counter before halting the computer, so as to determine where execution would commence from once the computer was restarted.
The TSX (Transfer and Set Index) instruction jumps to the location indicated by the address portion of the instruction, and stores the two's complement of its own location in the index register specified. This served as a subroutine jump instruction, since an indexed jump to location 1 would return to the instruction following the TSX instruction.
TTR (Trap Transfer) is a special jump instruction that ignores trapping mode.
CAS (Compare Accumulator with Storage) takes the next instruction if the operand is less than the accumulator, skips one instruction if both are equal, and skips two if the operand is greater than the accumulator. Plus zero is treated as greater than minus zero.
SXD (Store Index in Decrement) stores the contents of the specified index register in the bits of the accumulator corresponding to the decrement part of an instruction. If multiple index registers are specified, not only will the logical OR of the contents of those index registers be stored in that field of the accumulator, the index registers involved will also all contain the OR of their original contents. Note that this caution only applies in Multiple Tag Mode on a 7094. PXD (Place Index in Decrement) functions the same way, but also clears the rest of the accumulator except for the decrement portion.
VLM (Variable Length Multiply) uses the contents of the count field to indicate how many of the least significant bits of the MQ are to be multiplied by the memory operand; the product is aligned with the most significant bit of the magnitude portion of the accumulator, and thus it extends into as many of the most significant bits of the MQ as there were the least significant bits of it used in the multiplication.
The VDH and VDP instructions use the count field to indicate how many of the least significant bits of the MQ register will be used for the quotient, with the accumulator and the remaining bits of the MQ register being used for the remainder, in a division of (AC,MQ) by the memory operand. This allows divisions to be performed which would otherwise result in a divide check.
The PAI (Place Accumulator in Indicators) instruction places the contents of the accumulator in a special Sense Indicator register. The RIS instruction sets the contents of the SI register to their former value and the one's complement of the storage operand's contents. The TIO instruction jumps if SI and ACC equals ACC, the TIF instruction jumps if SI and ACC equals zero.
Three convert instructions were introduced with the IBM 709 computer. The CRQ instruction replaces the six-bit characters in the MQ, from left to right, as follows:
The address portion of the instruction points to a table in memory used to replace the first character. This is a table that is 64 words long. The first six bits of the word indicated by the first character (considered as a number from 0 to 63, indicating an entry) replace the first character. The last 15 bits of that same word indicate the address of the table to be used for the next character.
The count portion of the instruction indicates how many characters are to be translated; the translation can repeat itself. If index register 1 is indicated by the tag field, the table address to be used after the last replacement is left in that index register.
The CVR instruction works the same way, except that it translates characters from right to left in the accumulator. Also, the first character will have the former value of the Q bit ORed with its replacement.
The CAQ instruction takes characters from the MQ, and adds the entire table entry to which they point to the accumulator. The last 15 bits are still used as the address of the next table also. As well, it is important not to allow the instruction to cause a carry into bit 19 of the accumulator (where the most significant bit counts as 0, and the following bits are numbered in order), or it will not work properly.
The ESNT instruction jumps to its destination address, and also disables access to the upper half of memory.
The Type E instructions are a special group of Type B instructions can be considered to be the operate instructions, which use the Address field to indicate operations to be performed on the registers, instead of an address:
CLM +0760...000 Clear Magnitude * LBT +0760...001 Low Order Bit Test PBT -0760...001 P Bit Test CHS +0760...002 Change Sign EFTM -0760...002 Enter Floating Trap Mode  * SSP +0760...003 Set Sign Plus SSM -0760...003 Set Sign Minus * ENK +0760...004 Enter Keys  LFTM -0760...004 Leave Floating Trap Mode  * ESTM -0760...005 Enter Select Trap Mode  * COM +0760...006 Complement Magnitude ECTM -0760...006 Enter Copy Trap Mode  * ETM +0760...007 Enter Trapping Mode * LTM -0760...007 Leave Trapping Mode * RND +0760...010 Round * LSNM -0760...010 Leave Storage Nullification Mode  * FRN +0760...011 Floating Round * DCT +0760...012 Divide Check Test LMTM +0760...016 Leave Multiple Tag Mode  * EMTM -0760...016 Enter Multiple Tag Mode  *
Asterisks mark the large number of instructions which were omitted on the 7040 and 7044.
In Trapping Mode, entered by ETM and left by LTM, normal jump instructions instead caused software interrupts, to allow the execution of a program to be traced.
PBT would skip the next instruction if the P bit is one. DCT clears the divide check indicator, and if it had not been on in the first place, skips the next instruction.
The ENK instruction copies the contents of the switch register on the front panel to the MQ.
In floating trap mode, floating-point overflow causes an interrupt; otherwise, it only sets an overflow flag, which was the way the 704 operated.
Nothing prevents one from selecting an index register to use with these instructions, and this allows the part of the opcode in the address field to be modified before use, changing the operation performed.
On the 7040 and 7044, additional opcodes were made available by changing the opcode of the STR instruction from three bits to twelve:
STR -1000 Store Location and Trap  VMA -1204 Variable Length Multiply and Accumulate  CCS -1341 Compare Character with Storage  MIT -134106 Storage Minus Test  PLT -134107 Storage Plus Test  PCS -1505 Place Character from Storage  SAC -1623 Store Accumulator Character  MSM -162306 Make Storage Sign Minus  MSP -162307 Make Storage Sign Plus  TSL -1627 Transfer and Store Instruction Location Counter  TMT -1704 Transmit 
Since the character instructions used the last three bits of the count field of the instruction to select one of six characters, the two unused values there, 6 or 7, were used to indicate other instructions.
Before the IBM 360 redefined what a computer should look like, the IBM 704 and its successors were extremely widely used, and served as the most common paradigm for a single-address fixed-word-length computer.
Thus, in documentation for the DDP 124 computer, Y is used as the symbol for the address field, the field indicating the index register is called the Tag field, and the bit indicating indirect addressing is called the Flag bit. This was true, as well, for the DDP 116 and its successors, such as the Honeywell 516 (the page bit was called the Sector bit). The RCA 110 didn't have indirect addressing, but it also preserved the other designations from the 7090.
Y was used for operand addresses even in documentation for the Control Data 924, the ASI 6020, the Varian 520i, the SCC 660, the Westinghouse 2500, and the PDP-1, which otherwise did not follow 704 notation.
The floating-point formats for many 36-bit computers followed that of the 704, and the size of its exponent field is still that used by 32-bit floats in the IEEE 754 standard.
The DDP-24, 124, and 224 also used sign-magnitude representation for integers, like the 7090, and this fact was even used as a selling point in advertising at one point.
The widespread basic convention that assembler opcode mnemonics should all be three letters long, instead of being shorter where possible (following the 360) also appears to derive from the 704.