Instructions longer than 32 bits may be present in blocks with a header in the Type I, Type II, or Type IV formats. Thus, they are like unpaired short instructions; 16-bit short instructions may appear in blocks with a Type I or Type IV header, and 17-bit short instructions may appear in blocks with a Type I or Type II header.
The formats of 48-bit instructions are shown below: in these instructions,
the first three bits are 110, to indicate that the instruction is longer than 32 bits,
and the next two bits may have any value except 11 to indicate that the instruction
is specifically 48 bits long.
Note that among the memory reference instructions shown in lines 9 through 13, there are memory-to-register operate instructions, which is why a C bit is present, some of which are included in the 32-bit instruction set as supplemental memory-reference instructions of the second kind, and there are memory-to-registers acting on types of data other than the most basic types, some of the load and store instructions among which are included in the 32-bit instruction set as supplemental memory-reference instructions of the first kind.
Also note the presence of a bit marked as S. This bit is used to indicate scaled indexing; if the instruction is indexed, and the type of operand of the instruction is other than byte, the value in the index register is shifted left before use by as many places as appropriate so that the index is in units of the operand length; one place for halfwords, two places for integer and floating values, three places for long and double values, and four places for quad values. In the case of Medium floating-point operands, a shift of one place to the left is applied in accordance with their alignment, as opposed to attempting to multiply by six during address calculation.
In lines 14 through 18, additional memory reference instructions are shown. These have a shorter opcode, and thus they provide a more limited set of operations, but they contain a three-bit scaled field. This indicates the number of places the value taken from the index register is to be shifted left before use; in this way, index scaling is not limited to operand size, but may also refer to structures containing values, as long as the displacement is a power of two and not overly large.
Packed decimal and string instructions also perform operations, and the instructions of these types which are 64 bits long or longer do have a C bit. The 48-bit form of these instructions, however, does not include a C bit, and thus does not have the option of affecting the condition codes, because room for that bit was not available.
The formats of 64-bit instructions are shown below: in these instructions, the leading 110
is followed by 110 to indicate that the instruction is 64 bits long.
The reason that one bit of the instruction is interposed before the sequence of bits that indicates the length of the instruction is apparent from the diagrams: since that sequence of bits varies in length, having a bit of the instruction precede the sequence allows that bit to be used as the C bit for operate instructions, which indicates whether the instruction is allowed to set the condition codes, and that allows that bit to have the same position for all instructions of this type.
The 80-bit un-indexed three-operand string translate instruction is shown below:
and then the fully-indexed 96-bit translate instruction:
In CISC mode, the 48-bit instructions are only as shown in the diagram below:
Also, the 64-bit instructions are limited to those shown in this diagram:
Note that only the source operand may now be indexed for string and packed decimal operations.
Instructions 80 bits in length and longer are unchanged, except for their leading bits, as shown in the following table:
Standard CISC
80 bits 11011100 11111110
96 bits 110111100 111111110