The 17-bit instructions are made available when a block starts with a header of Type II, Type IV, Type VII, and Type VIII.
The instructions to be described in this section have the formats shown in this diagram:
These instructions allow any two registers to serve as the operands for the register-to-register operate instructions in line 1, and allow an eight-bit displacement for the branch instructions in line 6.
Line 1 gives the format of the operate instructions. Integer instructions reference the integer registers, and floating-point instructions reference the floating-point registers, as might be expected.
There are 96 possible opcodes, as the first two bits of an opcode may not be both 1, as these combinations are reserved for other 17-bit instructions.
The opcodes (with the first four bits appearing along the top of the chart, and the last three bits appearing on the right) are:
0 10 20 30 40 50 60 70 100 110 120 130
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011
SWB IB SWH IH SW I SWL SWM SWF SWD SWQ 000 0
CB CH C CL CM CF CD CQ 001 1
LB ULB LH ULH L UL LL LM LF LD LQ 010 2
XB XH X XL 011 3
AB NB AH NH A N AL NL AM AF AD AQ 100 4
SB OB SH OH S O SL OL SM SF SD SQ 101 5
MH MEH M ME ML MEL MM MF MD MQ 110 6
DH DEH D DE DL DEL DM DF DD DQ 111 7
The different instructions are:
For integer types:
M MULTIPLY Multiply the contents of the source and destination locations, placing the
least significant part of the result of the same length as the two input
operands in the destination location, with sign extension if that is shorter
than the length of the destination register
D DIVIDE Divide the contents of the source location by the contents of the destination
location, placing the quotient in the destination location
L LOAD Place the contents of the source operand in the destination register;
if the type involved is smaller than the register, perform sign extension
ST STORE Fill the destination location from the least significant part of the
source location
A ADD Add the contents of the source and destination locations, placing the
result in the destination location
S SUBTRACT Subtract the contents of the source location from those of the destination
location, placing the result in the source location
SW SWAP Exchange the contents of the source and destination locations
C COMPARE Subtract the contents of the source location from the contents of
the destination location, but with the operation modified so that
overflow cannot possibly result, and set the condition codes appropriately
without modifying the destination location
I INSERT Fill the least significant bits of the destination register with
the contents of the source location, leaving the rest of the destination
register unaffected
UL UNSIGNED LOAD Fill the least significant bits of the destination register with
the contents of the source location, and clear the remaining more
significant bits of the destination register
X EXCLUSIVE OR Perform a bitwise Exclusive OR operation between the contents of the source
and destination locations, placing the result in the desination location
N AND Perform a bitwise Logical AND operation between the contents of the source
and destination locations, placing the result in the desination location
O OR Perform a bitwise Logical OR operation between the contents of the source
and destination locations, placing the result in the desination location
ME MULTIPLY EXTENSIBLY Multiply the contents of the source and destination locations. Take the
full product, as an integer having twice the size as that of the source
and the destination, and:
- in the case of the halfword and integer versions of the instruction, place it in the destination
register, with sign extension in the halfword version;
- in the case of the long version of the instruction, place the most significannt half of the result
in the destination register, which must be an even-numbered register, and place the least significant
half of the result in the register following
DE DIVIDE EXTENSIBLY Divide a destination operand of twice the length of that indicated by the
instruction type (and located as the result of the MULTIPLY EXTENSIBLY
instruction) by the source operand; store the double length quotient
in the destination location (again following the MULTIPLY EXTENSIBLY
result placement) and the single length remainder in the next register
following those that are used.
Whenever a result is not wide enough to fill a register, sign extension
is performed.
Division is performed giving a result as if both operands were converted
to positive numbers before starting, with the signs then set afterwards
to give a correct result based on the actual signs of the operands. Thus
both the quotient and the remainder will be positive or zero if the dividend
and divisor have the same sign, and both will be negative or zero if they
are of opposite signs.
The possible integer types, and the suffixes that indicate them, are:
B BYTE An 8-bit two's complement integer
H HALFWORD A 16-bit two's complement integer
INTEGER A 32-bit two's complement integer
L LONG A 64-bit two's complement integer
The integer registers are 64 bits long, to contain the longest of these types.
The available floating-point operations are SWAP, LOAD, STORE, ADD, SUBTRACT, MULTIPLY, and DIVIDE. Their functions are basically the same as those of the corresponding integer operations, except that floating-point arithmetic is performed.
The possible floating-point types for 16-bit instructions, and the suffixes that indicate them, are:
M MEDIUM A 48-bit floating-point number (preferably aligned on 16-bit boundaries) F FLOATING A 32-bit floating-point number D DOUBLE A 64-bit floating-point number Q QUAD A 128-bit floating-point number
with their formats as indicated within this diagram:
Note that in the diagram, exponents for the types other than the 128-bit internal type are given as excess-126, excess-510, and excess-1022; documentation for the IEEE 754 standard, and most descriptions of it, refer to the exponents as excess-127, excess-511, and excess-1023 instead. This is because these accounts place the binary point of the mantissa in front of its first visible bit, while I place it in front of the hidden first bit to remain in accord with the convention used in most other floating-point formats that the mantissa is in the range [0.1). In the case of the 128-bit internal form, as the first bit of the mantissa is now the bit which would have been the hidden bit, since for the other forms, I had been placing the binary point in front of the hidden bit, the offset is consistent by remaining two less than a power of two; this would need to be the case even if I had used the normal convention for the exponents of the other formats.
Originally, it had been planned to have the 128-bit type of this architecture to be similar to 80-bit temporary real, but with a longer mantissa. In response to the new standard for a 256-bit floating type, what has been done is to make the exponent field of the 128-bit floating type of this architecture one bit larger than that of the new standard 256-bit floating-point type (in order to be able to handle its denormals correctly).
This means that instructions other than the short ones described on this page will be available to support the old 80-bit temporary real format, and the new standard 128-bit and 256-bit floating-point formats, but the internal form of a standard 128-bit floating-point number will require the use of more than one register, and the internal form of a standard 256-bit floating-point number will require the use of more than two registers.
These instructions are then also suffixed RC for Register Compact to indicate the addressing mode.
Lines 2 through 5 of the diagram illustrate the shift and rotate short instructions. These are:
30x00x LSLLC Logical Shift Left Long Compact
30x04x LSRLC Logical Shift Right Long Compact
30x10x RLLC Rotate Left Long Compact
30x14x ASRLC Arithmetic Shift Right Long Compact
32x00x LSLC Logical Shift Left Compact
32x04x LSRC Logical Shift Right Compact
32x10x RLC Rotate Left Compact
32x14x ASRC Arithmetic Shift Right Compact
33000x LSLHC Logical Shift Left Halfword Compact
33004x LSRHC Logical Shift Right Halfword Compact
33010x RLHC Rotate Left Halfword Compact
33014x ASRHC Arithmetic Shift Right Halfword Compact
33400x LSLBC Logical Shift Left Byte Compact
33404x LSRBC Logical Shift Right Byte Compact
33410x RLBC Rotate Left Byte Compact
33414x ASRBC Arithmetic Shift Right Byte Compact
Logical right and left shifts insert zeroes; the arithmetic right shift inserts a copy of the existing value of the most significant bit into the leftmost position of the word so as to maintain the sign as either negative or non-negative.
An arithmetic left shift inserts zeroes into the leftmost end of a number regardless of its sign, just like a logical left shift, but it differs in that the overflow bit is set if a left shift results in a change of the sign of the value being shifted, instead of merely a carry out of that value; this difference is, however, not applicable to short instructions, as they may not alter the condition codes, not having space for a C bit.
Line 6 of the diagram shows the branch instructions, which have the following opcodes:
3404xx BL Branch if Low
3410xx BE Branch if Equal
3414xx BLE Branch if Low or Equal
3420xx BH Branch if High
3424xx BNE Branch if Not Equal
3430xx BHE Branch if High or Equal
3434xx BNV Branch if No Overflow
3440xx BV Branch if Overflow
3450xx BC Branch if Carry
3454xx BNC Branch if No Carry
3474xx B Branch
Unused values are used instead for the set flag instructions in line 7, as follows:
3400xx CTF Condition to Flag Set flag to 1 if condition valid; set flag to 0 if condition not met
3460xx SFC Set Flag on Condition Set flag to 1 if condition met; leave it unaffected otherwise
3464xx CFC Clear Flag on Condition Set flag to 0 if condition met; leave it unaffected otherwise
Line 8 of the diagram shows the format of a special instruction:
3470xx SVC Supervisor Call
This instruction performs the equivalent of an interrupt from within software, allowing portions of the operating system not running in supervisor state to request services from the kernel, as well as possibly also allowing user programs to request services from the operating system.
15-bit short instructions are made available in instruction slots which start with
11 so as to permit the use of short instructions in blocks that
begin with a header of Type IV, Type VI, or Type VII, these being the types of headers which
do not permit code with variable-length instructions. As a result of that, 15-bit
short instructions always occur in pairs within a single fixed-length 32-bit
instruction word.
The format of these short instructions is shown below:
These instructions are very similar in format to the 17-bit short instructions.
One important change is that the shift instructions, in lines 3 through 6, can only operate on the contents of the first eight registers, registers 0 through 7.
The register-to-register instructions in line 1 are changed.
A two-bit page field is shared between the source and destination registers within the second of the two instructions present; it supplies the two most significant bits of the register number for both the source and destination registers, while the source and destination register fields supply the three least significant bits of the register number for those registers respectively.
This allows these register-to-register instructions to access all the registers, but the registers are divided into four groups of eight registers, and both operands of such an instruction must belong to the same one of these groups.
|
Paired 15-bit instructions may also be used in instruction blocks that
do not begin with a header, but only in instruction slots
other than the first one (in which the bits When one avails oneself of this option, one can think of the 32-bit instruction in the first instruction slot of the block as functioning as a "type zero" header which indicates a headerless block; this way of viewing the situation may, in fact, be useful to implementors of this architecture. And, of course, the Type III header is a precedent for the fact that a header may also be executable code as well. |
In blocks with a Type III, Type V, or Type VI header, if the A bit is set, a modified form of paired short instructions is available, with the format shown in the diagram below:
The first instruction in the instruction word is 15 bits long, with a 5-bit opcode, and performs a floating-point operation. The second instruction is 16 bits long, with a 6-bit opcode, and performs an integer operation. Since these instructions will, in most implementations, use different register banks, and different ALUs, this means that they can be relied upon to be able to execute in parallel, thus not requiring an additional B bit to indicate whether or not the second short instruction can execute in parallel with the first, therefore making this paired short instruction format better suited to use with the Type VI header in particular.
Other types of short instructions, such as shift instructions or conditional branch instructions, are not available in this format.
The 16-bit short instructions are used with the Type I header.
They are identical in capability to, although different in format from, the paired 15-bit short instructions, except that in addition they permit the use of a condition code bit with the two-operand register-to-register operate instructions.
Their format is as shown below:
The Type VIII header includes an R bit, which allows it to change from providing access to 17-bit short instructions and 35-bit instructions to instead provide access to 18-bit short instructions and 33-bit instructions.
The purpose of this is to give the short instructions, instead of the memory-reference operate instructions, the ability to change the condition codes.
These instructions have the format shown in this diagram:
These instructions are very similar to the 17-bit short instructions, but the bits of the register-to-register operate instructions had to be rearranged in order to allow the C bit to occupy its standard position.