The instructions to be described on this page have the formats, taken from the main illustration of instruction formats on the first page of this section, shown in this diagram:
These are the five types of 32-bit memory-reference instructions.
The 32-bit form of basic load and store instructions is shown in lines 1 through 5.
For a memory-reference instruction, the five-bit destination register field specifies one of 32 registers, either the general-purpose registers for integer instructions, or the floating-point registers for floating-point instructions.
The index register field contains a number from 0 to 7, if it contains 0, the instruction is not indexed; if it contains any other value, that value indicates which general register is to be used as the index register for that instruction.
Lines 1 through five show the five possible formats for 32-bit memory-reference instructions.
In line 1, a field three bits in length indicates the base register. It may contain any value from 1 to 7, which indicates that a general register from 25 to 31 respectively is used as the base register.
Line 2 of the original diagram shows the second possibility: a 15-bit displacement is included in the instruction, and general register 24 contains the starting point of the 32,768-byte area of memory to which the values of this displacement may refer.
Line 3 of the original diagram shows the third possibility. Here, the displacement is 12 bits long, and there is a three-bit ssB field (short source base) adjacent to it.
If that field contains a number from 1 to 7, it indicates that a register from 17 to 23, respectively, is used as a base register, the contents of which point to a 4,096-byte area in memory.
If that field contains a 0, then one of the possibilities shown in lines 4 and 5 of the diagram apply.
Line 4 of the original diagram shows the first of these possibilities: if the ssB field, containing a 0, is followed by a 0, then program-relative addressing is indicated.
The instruction now contains an 11-bit displacement, which is in units of bytes, but now it is a signed two's complement value from -1,024 to 1,023, relative to the position immediately after the end of the instruction. One particularly important application of this addressing mode is at the beginning of a main program or a subroutine, where a Jump to Subroutine instruction having the following instruction as its destination can be used to initialize a base register by means of which adresses referring to the program code can be constructed.
Line 5 of the original diagram shows the format for two other addressing modes.
If the ssB field, containing a 0, is followed by 100, then it indicates Array Mode addressing.
Here, the contents of register 17 are added to the displacement, which is now in units of 64 bits or eight bytes, to indicate the location of a 64-bit pointer to an array.
If indexing is present in the instruction, the contents of the selected register are added to that pointer in order to address an element of that array. Thus, Array Mode provides post-indexed indirect addressing in order to conveniently allow a program to refer to up to 512 arrays which are larger than 65,536 bytes in size without having to reload base registers in order to access them.
If the ssB field, containing a 0, is followed by 101, then Address Table addressing is indicated.
Here, the contents of register 17 are added to the displacement, which is now in units of 64 bits or eight bytes, to indicate the location of a 64-bit constant containing the effective address of the instruction.
If indexing is present in the instruction, the contents of the selected register are added to the initial effective address formed by adding the contents of register 17 to the displacement, so as to change which 64-bit constant is taken as the effective address.
Thus, Array Mode addressing provides pre-indexed indirection, and Address Table addressing provides post-indexed indirection. Array Mode addressing is useful for accesing data in multiple large arrays without reloading base registers, and Address Table addressing is useful for such things as multi-way jump tables.
If the ssB field, containing a 0, is followed by 110, then Array Mode with Auto-Increment addressing is indicated. The displacement is in units of 64 bits, and the contents of base register 17 are added to the displacement after scaling to find the address to be used; this address may be indexed to form the effective address, and, in addition, after the memory location at the effective address so calculated is accessed, the index register is then incremented by the size of the operands of the instruction; incremented by one if the instruction acts on bytes, having eight added to it if the instruction acts on double-precision floating-point numbers, and so on. This includes adding six in the case of medium floating-point numbers.
If the ssB field, containing a 0, is followed by 111, then Array Mode with Flexible Auto-Increment addressing is indicated. Here, if the instruction is indexed, the index register must be one of registers 2, 4, or 6, and the amount by which it is incremented after memory access is found in the following register.
At this point, it may be noted that one programming technique that is not available in this Instruction Set Architecture (ISA) is to insert data in the locations immediately following a Jump to Subroutine instruction, so that the called routine can retrieve parameters in that data, and then increment the return pointer before using it to return so that the data is skipped over.
This also means that one cannot embed a routine name immediately following the initial Jump to Subroutine instruction used for initializing the first base register as a way to facilitate documentation of errors.
That is because of how instructions are organized: in 256-bit blocks which consist of 32 or 64 bits of header information, followed by 32 to 224 bits of pure 32-bit instructions, with immediate values and other additional portions of those instructions placed after the instructions.
It is intended that compilers and assemblers will treat the supplementary portions of instructions as aligned on 16-bit boundaries, and will order immediate data by placing the items with the largest alignment width at the end of the block, and then the items with the next-largest alignment width in front of them, and so on. This way, all the immediate data will be correctly aligned, so as to be consistent with the maximum speed of operation. In most cases, this means the widest items are placed at the end, but 48-bit Medium floating-point numbers, this length being only a multiple of 16 bits, have an alignment width of 16 bits and so are treated as "shorter" than 32-bit items in this sense.
The opcodes of the basic memory-reference instructions are:
000xxx xxxxxx LB Load Byte 004xxx xxxxxx STB Store Byte 010xxx xxxxxx ULB Unsigned Load Byte 014xxx xxxxxx IB Insert Byte 020xxx xxxxxx LH Load Halfword 024xxx xxxxxx STH Store Halfword 030xxx xxxxxx ULH Unsigned Load Halfword 034xxx xxxxxx IH Insert Halfword 040xxx xxxxxx L Load 044xxx xxxxxx ST Store 050xxx xxxxxx UL Unsigned Load 054xxx xxxxxx I Insert 060xxx xxxxxx LL Load Long 064xxx xxxxxx STL Store Long 070xxx xxxxxx LA Load Address 100xxx xxxxxx LM Load Medium 104xxx xxxxxx STM Store Medium 110xxx xxxxxx LF Load Floating 114xxx xxxxxx STF Store Floating 120xxx xxxxxx LD Load Double 124xxx xxxxxx STD Store Double 130xxx xxxxxx LQ Load Quad 134xxx xxxxxx STQ Store Quad
The Load Address instruction places the effective address of the instruction in the destination general register, instead of loading a value at the effective address from memory.
A fixed-point Load instruction, when the operand type is shorter in length than the register in which it is to be placed, performs sign extension. The Unsigned Load instruction performs zero extension instead, and the Insert instruction leaves the bits to the left of the operand being loaded unaffected.
The conditional jump instructions, shown on line 21, have the opcodes:
15541x xxxxxx JL Jump if Low 15542x xxxxxx JE Jump if Equal 15543x xxxxxx JLE Jump if Low or Equal 15544x xxxxxx JH Jump if High 15545x xxxxxx JNE Jump if Not Equal 15546x xxxxxx JHE Jump if High or Equal 15547x xxxxxx JNV Jump if No Overflow 15550x xxxxxx JV Jump if Overflow 15552x xxxxxx JC Jump if Carry 15553x xxxxxx JNC Jump if No Carry 15557x xxxxxx J Jump
These instructions cause a transfer of control to the instruction located at the effective address of this instruction. As the displacement is a byte value, transfer of control to the second of two 16-bit instructions is possible.
In these instructions, the base register field is its normal three bits in length, with the values 1 through 7 in this field indicating the use of the general registers 25 through 31 respectively as the base register. A value of zero functions in the same way as it does in the case of a two-bit field.
The available addressing modes for these instructions are the same as those for the memory-reference instructions as shown in lines 1 through 4, but they are not repeated in the illustration.
The subroutine jump instruction, shown on line 6, has the opcode:
070xxx xxxxxx JSR Jump to Subroutine
In addition to branching to the effective address of the instruction, it stores a return address in the register indicated by the return register field.
The default value of the return address is the address of the next 32-bit instruction slot following the instruction. The instruction also includes an offset field; its contents, if nonzero, are shifted one place to the left (so that they are in units of 16 bits) and added to the return address.
In this way, in the case where a Jump to Subroutine instruction is in the last 32-bit instruction slot used for instructions in a given block, the return address can be made to point directly to the next instruction to be executed, even if the following block begins with a header.
Note that the 32-bit subroutine jump may not be indexed.
Lines 7 and 8 illustrate the format of the 32-bit version of the basic multiple register memory reference instructions, and lines 9 and 10 illustrate the format of the 32-bit version of the multiple memory-reference instructions for short vectors.
Due to the limited available space in a 32-bit instruction, only two of the five formats for indicating a memory address are used:
in line 6, the same one as shown in line 2, and in line 7, the same one as shown in line 3.
Also, indexing is not available with the 32-bit form of these instructions.
The available instructions in this format are:
140xxx LML Load Multiple Long 142xxx STML Store Multiple Long 144xxx LMQ Load Multiple Quad 146xxx STMQ Store Multiple Quad 1500xx LMSV Load Multiple Short Vector 1504xx STMSV Store Multiple Short Vector
The load and store multiple long instructions load and store the 64-bit contents of the specified integer registers, in successive locations at the destination address.
The load and store multiple quad instructions load and store the 128-bit contents of the specified floating-point registers.
The load and store short vector registers load and store the 256-bit contents of the specified short vector registers.