Instructions longer than 32 bits, like 17-bit instructions, may only be present in
blocks that either begin with the four bits 1110, which is followed by a
sequence of fourteen pairs of bits, each of which constitutes a prefix
field, associated with each of the 16-bit halves of the remaining 32-bit instruction slots in the block,
or or with the related form of block header which instead associates a three bit
prefix with every 16 bits remaining in the block, so as to provide even more flexibility.
These header formats are illustrated as the formats of type III and type IV in the diagram below, which also appeared on the first page of this description of the Concertina II architecture:
An additional constraint is present for instructions that are 48 bits in length; these instructions may only appear in a block with a type IV header. This is because long instructions of this length are not distinguished internally by leading bits from standard 32-bit instructions, in order that they may have more opcode space.
In the case of a Type III header, the contents of the prefix field have the following values:
0 followed by another bit, which signifies that the second bit of the prefix
field is the first bit of a 17-bit instruction, the remaining bits of which are in the corresponding 16 bits
of the block;
10, which signifies that the corresponding 16 bits in the block are the first 16 bits of
an instruction; and
11, which indicates that the corresponding 16 bits in the block do not begin an instruction,
and may be later bits in an instruction, or space used for a pseudo-immediate value, or space that is either
unused or used for some other purpose.
Normally, when the prefix bits are 10, then the corresponding 16 bits in
the block will be the first half of a 32-bit instruction, but they may also be the first 16 bits of an
instruction 48 bits long or longer.
In this case, the first three bits of the instruction will be 111, as this bit pattern is
available from the 32-bit instructions, given that 1110 begins a header, and 1111
begins a pair of 15-bit instructions, not needed because now 17-bit instructions are available.
Some opcode space left by unused 15-bit instructions is used for the type II, type V, and type VI headers, but these are also not used in instruction slots other than the first one.
In the case of a type IV header, the different values for the prefix bits have the following meanings:
000 a 17-bit instruction starting with 0 001 a 17-bit instruction starting with 1 010 not used in this header format 011 not the start of an instruction 100 the start of a normal 32-bit instruction 101 alternate 32-bit instruction 110 a 33-bit instruction starting with 0 111 a 33-bit instruction starting with 1
Here, only the prefix bits 010 may be used to indicate the first 16 bits of an instruction
longer than 32 (or really 33) bits, so that any 32-bit instructions that start with 111 become
available with the normal 32-bit instructions as indicated by the prefix bits 100.
Note, however, that a 48-bit instruction that crosses block boundaries may cross over into a block with a type III header, even though such an instruction may not start within such a block.
The formats of 48-bit instructions are shown below: in these instructions,
the first three bits are 111, to indicate that the instruction is longer than 32 bits,
and the next two bits may have any value except 11 to indicate that the instruction
is specifically 48 bits long.
Note that among the memory reference instructions shown in lines 9 through 13, there are memory-to-register operate instructions, which is why a C bit is present, some of which are included in the 32-bit instruction set as supplemental memory-reference instructions of the second kind, and there are memory-to-registers acting on types of data other than the most basic types, some of the load and store instructions among which are included in the 32-bit instruction set as supplemental memory-reference instructions of the first kind.
Also note the presence of a bit marked as S. This bit is used to indicate scaled indexing; if the instruction is indexed, and the type of operand of the instruction is other than byte, the value in the index register is shifted left before use by as many places as appropriate so that the index is in units of the operand length; one place for halfwords, two places for integer and floating values, three places for long and double values, and four places for quad values. In the case of Medium floating-point operands, a shift of one place to the left is applied in accordance with their alignment, as opposed to attempting to multiply by six during address calculation.
Packed decimal and string instructions also perform operations, and the instructions of these types which are 64 bits long or longer do have a C bit. The 48-bit form of these instructions, however, does not include a C bit, and thus does not have the option of affecting the condition codes, because room for that bit was not available.
The formats of 64-bit instructions are shown below: in these instructions, the leading 111
is followed by 0 to indicate that the instruction is 64 bits long.
In these diagrams, the prefix bits associated with each 16 bits of the instruction are shown raised on the left, followed by the 16 bits of the instruction to which they correspond.
The reason that one bit of the instruction is interposed before the sequence of bits that indicates the length of the instruction is apparent from the diagrams: since that sequence of bits varies in length, having a bit of the instruction precede the sequence allows that bit to be used as the C bit for operate instructions, which indicates whether the instruction is allowed to set the condition codes, and that allows that bit to have the same position for all instructions of this type.
The 80-bit un-indexed three-operand string translate instruction is shown below:
and then the fully-indexed 96-bit translate instruction:
