Welcome to the home page of the Concertina IV computer architecture.
The original Concertina computer architecture was originally intended as a simple example of a conventional old-style CISC architecture, to help explain how computers work. It was expanded over time to include many features from a wide selection of historical computer architectures, to explain those as well.
Concertina II was intended as an ISA that could conceivably be of practical use in an actual implementation. One of its features, however, was much criticized; the organization of instructions into blocks 256 bits long, which could optionally begin with a block header that affected the interpretation of instructions within that block.
Concertina III attempted to remove that feature, at the cost of using banks of 16 registers for integer and floating-point registers rather than banks of 32 registers. This, however, led to the loss of some features that Concertina II was able to make available, over and above the inevitable loss of the availability of VLIW features, such as predication and the explicit indication of parallelism.
Concertina IV, therefore, attempts to return to banks of 32 registers. This goal seemed tantalizingly close to possibility after sketching out its predecessor. This allows the return of extended register banks of 128 registers and 20-bit long displacements. However, while it was possible to achieve this, it did not come without a cost.
One of the most valuable features of an ISA with variable-length instructions is the ability to have instructions shorter than 32 bits, so as to allow programs to be compact. But with banks of 32 registers, opcode space was extremely limited, and 16-bit instructions versatile enough to be genuinely useful would require a lot of opcode space.
Given that short instructions providing all the features desirable for even a minimal version of register-to-register operate instuctions would need to be 18 bits long, given banks of 32 registers, and indicating the length of instructions by their first few bits means that one looks for an instruction wherever the preceding instruction ends... the way to proceed was obvious, even though it required accepting something I had wished to avoid.
In Concertina IV, instructions may begin at any byte location, because the architecture includes 24-bit short instructions. There are also 16-bit short instructions, but these are limited to operating on the first eight registers of each register bank.
The extreme pressure on opcode space resulting from attempting to have such features as full base-index addressing combined with banks of 32 registers has resulted in a degree of fragmentation of opcode space. Opcode space in Concertina IV is basically organized as follows:
0 32-bit instructions 10 32-bit instructions 110000 32-bit instructions (Halfword Immediate) 110001 24-bit short instructions 11001 64-bit instructions 1101 48-bit instructions 1110 16-bit short instructions 11110 16-bit short instructions 11111 80-bit instructions
except that the first line in this list isn't quite accurate, because additional lengths of instructions are squeezed into the area shown as belonging to it, as follows:
0111110110 96-bit instructions 0111110111 160-bit instructions 0111111 144-bit instructions
The basic complement of registers included with this architecture is as follows:
There are 32 integer registers, each of which is 64 bits in length, numbered from 0 to 31.
Registers 1 through 7 may be used as index registers.
Registers 25 through 31 may be used as base registers, each of which points to an area of 65,536 bytes in length.
Register 24 serves as a base register which points to an area 32,768 bytes in length.
Registers 17 through 23 may be used as base registers, each of which points to an area of 4,096 bytes in length.
At least part of the area of 3,072 bytes in length pointed to by register 16 will normally be used to contain up to 384 pointers, each 64 bits in length, for use in either Array Mode addressing or Address Table addressing.
Registers 9 through 15 may be used as base registers, each of which points to an area of 1,048,576 bytes in length. This addressing format is used for 48-bit extended memory-reference instructions.
Register 8 serves as a pointer to a table of pseudo-operations, if this feature is used.
There are 32 floating-point registers, each of which is 128 bits in length, numbered from 0 to 31.
Floating point numbers in IEEE 754 format have exponent fields of different length, depending on the size of the number. For faster computation, floating-point numbers are stored in floating-point registers in an internal form which corresponds to the format in which extended precision floating-point numbers are stored in memory: with a 15-bit exponent field, and without a hidden first bit in the significand.
As 128-bit extended floating-point numbers are already in this format in memory, all floating-point numbers will fit in a 128-bit register, although shorter floating-point numbers are expanded.
However, the 32 floating-point registers may also be used for Decimal Floating-Point (DFP) numbers. These numbers will also be expanded into an internal form for faster computation, but that internal form may take more than 128 bits.
This is dealt with as follows: Only 24 DFP numbers that are 128 bits in length may be stored in the 32 floating-point registers. When such a DFP number is stored in an even-numbered register, it is stored in that register, and the first 32 bits of the following register. When it is stored in a register the number of which is of the form 4n + 1 for integer n, the first 84 bits of the internal form of that number are stored in the last 84 bits of that register, and the remainder of the internal form of that number is stored in the last 84 bits of the second register after that register.
In this way, the same principle that storing double-length numbers in two adjacent registers is respected: numbers too long to be stored in a given register are stored in that register, and in another register of the same register file that is nearby. But the method is extended to allow more efficient use of the available space.
The same technique is used for the 128-bit floating-point format which has recently been added to IEEE 754 which does have a hidden first bit; therefore, in order to support this format, the usual 128-bit floating-point format offered by this architecture, while similar to, and based on, the Temporary Real format of the original 8087 coprocessor, has an exponent field that is one bit longer than that of the Temporary Real format.
There are 16 short vector registers, each of which is 256 bits in length.
Each of these registers may contain:
As well, they may contain sixteen 16-bit short floating-point numbers in one of two formats.
These numbers all remain in these registers in the same format as that in which they appear in memory.
The entire set of 16 short vector registers can contain a table of bits used for bit-matrix-multiply operations on 64 bit binary words. As well, the short vector registers may also be used as four string registers, each 128 bytes in length.
This is done, rather than using them as two string registers, each containing 256 bytes, because four registers are the minimum number of registers required for the general register style of operations, at least as claimed in advertising literature for the Data General Nova. Having these strings only half the maximum length of those available to memory-to-memory string operations is presumed to be accessible, since strings "really" only have to be at least 80 characters long, as everyone knows.
In addition to the basic set of registers, two other larger sets of registers are also included in the architecture:
A set of 128 64-bit integer registers, and a set of 128 128-bit floating point registers.
A set of 8 vector registers, each of which contains 64 storage locations for floating-point numbers, each one 80 bits wide. This allows the computer to process vectors of 72-bit floating-point numbers in addition to vectors of 64-bit floating-point numbers, if the optional variable memory width feature is included.
As for how data values are stored in memory:
Signed integer values are stored in binary two's complement format.
Floating-point numbers are stored in IEEE 754 format, but in addition there are instructions for processing data in the format originally used by IBM's System/360 computers, including the Extended Precision format introduced on the Model 85.
The architecture is big-endian: the most significant bits of a value are stored in the byte at the lowest numbered address.
As well, there are 16 flag bits which are used for instruction predication, and of course there is a 64-bit program counter. The program status quadword includes eight alternate sets of condition codes in addition to the normal set of condition codes, and the program counter and flag bits are also part of the program status quadword.