The Simple Floating Type

Also with this prefix are a series of unusual floating-point arithmetic instructions which are performed using the integer arithmetic unit:

173703 110xxx  SFSWH Simple Floating Swap Halfword
173703 111xxx  SFCH  Simple Floating Compare Halfword
173703 112xxx  SFLH  Simple Floating Load Halfword
173703 113xxx  SFSTH Simple Floating Store Halfword
173703 114xxx  SFAH  Simple Floating Add Halfword
173703 115xxx  SFSH  Simple Floating Subtract Halfword
173703 116xxx  SFMH  Simple Floating Multiply Halfword
173703 117xxx  SFDH  Simple Floating Divide Halfword

173703 120xxx  SFSW  Simple Floating Swap
173703 121xxx  SFC   Simple Floating Compare
173703 122xxx  SFL   Simple Floating Load
173703 123xxx  SFST  Simple Floating Store
173703 124xxx  SFA   Simple Floating Add
173703 125xxx  SFS   Simple Floating Subtract
173703 126xxx  SFM   Simple Floating Multiply
173703 127xxx  SFD   Simple Floating Divide

173703 130xxx  SFSWL Simple Floating Swap Long
173703 131xxx  SFCL  Simple Floating Compare Long
173703 132xxx  SFLL  Simple Floating Load Long
173703 133xxx  SFSTL Simple Floating Store Long
173703 134xxx  SFAL  Simple Floating Add Long
173703 135xxx  SFSL  Simple Floating Subtract Long
173703 136xxx  SFML  Simple Floating Multiply Long
173703 137xxx  SFDL  Simple Floating Divide Long

These instructions involve pairs of registers, and operands twice the length of their associated integer type. They work on floating-point numbers represented as pairs of integers.

The first integer is the mantissa, which is a signed two's complement number, and the second integer is the exponent, which is also a signed two's complement number.

In the case of the simple floating long type, since a pair of arithmetic/index registers are required for a 64-bit value, the instructions work on groups of four registers. (Only a pair of registers is required in the case of the 64-bit supplementary arithmetic/index registers; but in that case, due to the arithmetic operations required, a pair of registers is still used in the case of operands of the shorter types as well.)

This allows the computer to match the capabilities of some early computers which used this basic method of achieving the ability to do floating-point arithmetic without adding extensive new logic for performing such arithmetic, most notably the Recomp II.

In addition, versions of the conversion instructions for this floating-point mode are provided here as well:

173703 1427xx 1xx1xx     CVPSFH    Convert Packed to Simple Floating Halfword
173703 1437xx 1xx1xx     CVSFHP    Convert Simple Floating Halfword to Packed
173703 1447xx 1xx1xx     CVPSF     Convert Packed to Simple Floating
173703 1457xx 1xx1xx     CVSFP     Convert Simple Floating to Packed
173703 1467xx 1xx1xx     CVPSFL    Convert Packed to Simple Floating Long
173703 1477xx 1xx1xx     CVSFLP    Convert Simple Floating Long to Packed

These instructions have the same format as the conversions between packed decimal and floating-point types, but, after the prefix, use a different portion of the available opcode space, the opcodes of the form 14x7xx instead of those of the form 14x5xx.

Note that, due to the large magnitudes possible with this floating-point format, execution times for these instructions may be longer than for the corresponding conversions to and from conventional floating-point types.

Simple floating operands in registers always begin with an even-numbered register: where the operand is of long type, since each of the elements occupies a pair of registers, only arithmetic/index registers 0 and 4 can be used as the source or destination of a long simple floating operation.

These operations, unlike the register packed operations, can be performed using the long vector arithmetic unit as well. This is particularly useful with the simple floating instructions (for which only long operations require the use of an even numbered register, since the supplementary arithmetic/index registers are 64 bits long, not 32 bits long) when the common floating-point format is selected, as it can increase by half the amount of floating-point operations that can be concurrent at a given instant.

This may not lead to the full expected corresponding speed increase, however, since some implementations may apply optimizations to the floating-point arithmetic units that are not applied to the integer arithmetic units. Also, for the long simple floating instructions, since it is envisaged little extra hardware will be added for this relatively little-used function, multiplications will require two steps rather than one, to make use of circuits designed only to multiply numbers of half the width of the complete number; this will be no problem for the ordinary simple floating-point format, but it will affect simple floating-point instructions when the format is modified to be the common floating-point format.

Instructions in the vector register mode that would normally handle up to 64 operands instead would handle up to 32 operands of the simple floating type, and are coded as if each simple floating operand is simply two successive integer operands. However, the start of a range must be even, the end of a range must be odd, and mask bits must be on or off in pairs, so that any simple floating value composed of two integers has both its parts either included or excluded from a given simple floating vector operation, or the results will be undefined.

Although it may appear that the simple floating halfword type is of limited utility, since a signed 16-bit number provides about four and a half decimal digits of precision, this type can be useful under some circumstances:

• when the word length is increased from 32 bits to 36 or 40 bits; a signed 18-bit number provides five decimal digits of precision, and single-precision floating point numbers on the Digital Equipment Corporation PDP-15 computer were of this type (whereas, for double-precision numbers, which occupied three words, the effort was made to split the first word into two halves, only the first of which was used for the exponent, with the result that single-precision floating-point numbers had a larger range than double-precision floating-point numbers);
• when the Common Floating-Point Format bits in the Program Status Block are not both zero, so that the length of the mantissa field is increased at the expense of that of the exponent field.

Because arithmetic on operands of the Simple Floating type is performed using the hardware primarily intended for integer arithmetic, not only are no guard bits retained in registers between operations on values of this type, but no guard bit or sticky bit is used with a value of this type during an operation. Therefore, the results even of simple operations on values of the Simple Floating type are not guaranteed to be the closest approximation to the correct result expressible in the format.

Only the Simple Floating type has the latter limitation, although the former limitation, of no guard bits retained between operations, is shared by some other floating-point types. The following table summarizes the situation.