This section is chiefly concerned with the instructions having prefixes belonging to the group 17377m.
At least one instruction performing what would seem to be a privileged operation lies outside this group, and has already been encountered: the SSIUM instruction, with opcode 171775, which sets the entire Program Status Block. However, when this instruction is executed outside of supervisor mode, it simply behaves like a SUSIUM instruction does when it attempts to set bits in portions of the Program Status Block denied by the Program Status Mask: the instruction is trapped if the mask happens to specify that bits are to be changed which the program is not allowed to change. While that applies to every bit that an SSIUM instruction can change that a SUSIUM instruction cannot, it may be that for some user mode programs the use of the SSIUM instruction will simplify operand alignment.
One group of instructions of this type, those which modify the Global Memory Map, will be discussed in the next section.
Having the same basic format as the load and store instructions, the input-output instructions deal with a separate address space to which no caching is applied. Of course, memory-mapped I/O and DMA are used for many input-output functions, but straightforwards input/output instructions are still useful to control or initiate DMA or other high-speed transfers.
173770 042xxx IN Input 173770 043xxx OUT Output
The eight 64-bit system registers can be accessed using instructions patterned after the multiple-register load and store instructions:
173770 152xxx LMSRR Load Multiple System Register Relative 173770 153xxx STMSRR Store Multiple System Register Relative 173770 154xxx LMSR Load Multiple System Register 173770 155xxx STMSR Store Multiple System Register 173770 156xxx LMSRSRR Load Multiple System Register System Register Relative 173770 157xxx STMSRSRR Store Multiple System Register System Register Relative
These instructions provide multiple register loads and stores for both the arithmetic-index registers and the system registers using the system registers instead of the base registers (LMSRR, STMSRR, LMSRSRR, STMSRSRR), and multiple register loads and stores for the system registers using the base registers (LMSR, STMSR).
For returning from an interrupt, the following instruction is provided:
173770 102xxx RFI Return From Interrupt
This memory-reference instruction accesses an operand which is 1,024 bits in length. The first 512 bits are loaded into the Program Status Block. The next 384 bits contain internal information in a possibly model-dependent format to permit a long instruction, interrupted during its performance, to be resumed after an interrupt. The final 128 bits contain 64-bit values to be placed in the two program counters.
Some necessary privileged instructions are highly model-dependent. An instruction will usually be needed to define, for a given Process ID, which portion, if any, of the on-chip register storage is used for each group of registers for that process.
It is possible, though, that an implementation might have a fixed allocation of register space to processes, and only permit process IDs 0 through 63 to be used. In such a case, instead of having a single continuous bank of register memory, each type of register would belong to its own space, and the allocation might be like this:
Process ID 0 - 1 Long Vector Scratchpad 0 - 1,
Long Vector Register Bank 0 - 1
Process ID 0 - 3 Supplementary Register Bank 0 - 3,
Explicit Bit-Matrix Multiply Register Bank 0 - 3
Process ID 0 - 31 Short Vector Register Bank 0 - 31
Base and Scratchpad Register Bank 0 - 31
Process ID 0 - 63 Floating Point Register Bank 0 - 63
Arithmetic-Index Register Bank 0 - 63
Process ID 32 - 63 Base Register Bank 0 - 31
where base registers can either be drawn from a bank of storage supplying a set of base registers only, or a bank of storage supplying a set of base registers together with a set of each of the three types of scratchpad registers.