The eight-bit field labelled mode of operation selects which, if any, of the alternate instruction modes is in use; the instruction modes are:
00000000: normal mode 7-bit 00000001: aligned operand mode 7-bit#/4-bit 13-bit/10-bit 00001000: extended operate mode 6-bit 00001011: aligned condensed mode 7-bit##/4-bit 13-bit/10-bit 00011000: symmetric address mode 7-bit 00011100: symmetric vector register mode 7-bit 00100000: stateless scratchpad mode 6-bit 00100001: register scratchpad mode 6-bit 00100100: double base mode 8-bit/5-bit 00100101: flexible register mode 6-bit** 00100111: simple compact mode 6-bit 00101000: stateful scratchpad mode 6-bit/4-bit 00101010: mutable scratchpad mode 6-bit/4-bit 00101100: plain stateful scratchpad mode 6-bit/4-bit 00101110: plain mutable scratchpad mode 6-bit/4-bit 00110000: vector register mode 7-bit*
Following the name of the mode, the length of the opcode field is indicated. The basic instructions of the machine are defined as having seven-bit opcodes. To make room for more addressing modes, some instruction modes provide only a six-bit opcode field in the instruction, and others provide only a four-bit opcode field to allow operand addresses to be contained within instructions that are only a single halfword in length.
The modes where the indication of the use of seven-bit opcodes is marked with an asterisk include the seven-bit opcode in instruction words in the following format: first the last five bits of the seven-bit opcode, and then, later in the instruction word, its first two bits.
When a seven-bit opcode is marked with two asterisks, this indicates it behaves like the last seven bits of an eight-bit opcode, and its two first bits, therefore, may be 11. Such opcodes are not treated as seven-bit opcodes for purposes of opcode translation.
Opcodes referred to as seven bits and marked with # also provide the range of operations of the last seven bits of an eight-bit opcode, but because they belong to aligned operand mode, the type of the operand is tied intimately to the format of the instruction, and so opcode translation is not possible. Opcodes of this type which have the range of operations of a conventional seven-bit operand are marked with ## and are indicated as seven bit opcodes.
An asterisk for 6-bit opcodes indicates the opcodes are not subject to opcode translation. Two asterisks indicates also a 6-bit opcode where the first two bits cannot be 11, like a normal 7-bit opcode.
Not shown in the table above are some additional modes termed as variant alignment modes. At this time, five such modes are defined:
01100000: aligned instruction mode 01100110: general register mode 01111000: three-address RISC mode 01111100: flexible CISC mode 01111101: stack machine mode
The first two of these align on 32-bit boundaries, and have normal seven-bit opcodes; the remaining three modes align on 8-bit boundaries, and opcode translation is not applicable to them, as they differ more considerably from the conventional instruction modes.
The three bits in the Program Status Block labelled six-bit opcode translation control how the first three bits of a six-bit opcode are expanded into the first four bits of the actual opcode of the instruction to be performed. This allows the selection, for a given program, of the appropriate subset of the available data types in the architecture. These bits also govern how five-bit opcodes are translated as well, expanding their first two bits into the first four bits of an effective seven-bit opcode.
In addition to the basic data types provided by the architecture, several other data types also exist that can be referenced within the framework of a memory reference instruction.
There are also types that cannot be so referenced, such as short vectors, which require the ability to specify mask bits, strings and packed decimal quantities, which require a length field, and long vectors, which require both length and a mask, but as they cannot be referenced within standard memory reference instructions, the current discussion is not concerned with them.
These types are the three simple floating types, simple floating halfword, simple floating, and simple floating long, the two register packed types, register packed and register packed long, and the compressed decimal versions of these types, the two decimal exponent floating-point types, decimal exponent medium and decimal exponent double. As well, unnormalized arithmetic on the conventional floating-point types as well as on the additional floating-point types is also made
These types can be accessed by the use of a 16-bit mode-independent instruction as a prefix to an instruction. In the case of a program that makes extensive use of these types, however, it may be useful to allow them to be specified within the opcode field itself, thereby making such programs shorter.
The three-bit field which specifies six-bit opcode translation, in addition to indicating various subsets of the conventional types accessible through the usual seven-bit opcodes which a six-bit opcode can indicate, may also take on values which include some of these additional types among those reachable with a six bit opcode.
The following table indicates the significance of the possible values of the three bit long field in the Program Status Block indicating the mode of six-bit opcode translation in use:
Six-Bit Opcode Translate Field Value
000 001 010 011
000 0000 Byte 0000 Byte 0010 Halfword 0010 Halfword
001 0001 0001 0011 0011
010 0010 Halfword 0100 Integer 0100 Integer 0100 Integer
011 0011 0101 0101 0101
100 0100 Integer 0110 Long 0110 Long 0110 Long
101 0101 0111 0111 0111
110 1001 Floating 1001 Floating 1001 Floating 1010 Double
111 1010 Double 1010 Double 1010 Double 1011 Quad
(five-bit opcodes)
00 0100 Integer 0110 Long 0010 Halfword 0100 Integer
01 0101 0111 0011 0101
10 1001 Floating 1001 Floating 1001 Floating 1010 Double
11 1010 Double 1010 Double 1010 Double 1011 Quad
Six-Bit Opcode Translate Field Value
100 101 110 111
000 0010 Halfword 0100 Integer 0000 Byte 0000 Byte
001 0011 0101 0010 Halfword 0001
010 0100 Integer 0110 Long 0100 Integer 0010 Halfword
011 0101 0111 0110 Long 0011
100 1000 Medium 1000 Medium 1000 Medium 0100 Integer
101 1001 Floating 1001 Floating 1001 Floating 0101
110 1010 Double 1010 Double 1010 Double 0110 Long
111 1011 Quad 1011 Quad 1011 Quad 0111
(five-bit opcodes)
00 1000 Medium 0010 Halfword 0000 Byte
01 1001 Floating 0100 Integer 0001
10 1010 Double 1001 Floating 0100 Integer
11 1011 Quad 1010 Double 0101
These normal translations are in effect for six-bit opcodes when either the three-bit additional type handling field in the Program Status Block is zero, or when the seven-bit translation mode bit in the Program Status Block is a one.
It is possible to modify how seven-bit opcodes are interpreted as well. These opcodes are subject to translation when the seven-bit translation mode bit in the Program Status Block is a one, and they are also subject to translation when the three-bit additional type handling field in the Program Status Block is not zero.
When the seven-bit translation mode bit in the Program Status Block is a one, then the three-bit six-bit opcode translation field, in addition to determining how six-bit opcodes are translated, performs the same translation on the last six bits of a seven-bit opcode which starts with 0. The additional type handling field then indicates how seven-bit opcodes which start with 10 are interpreted.
When the seven-bit translation mode bit in the Program Status Block is a zero, the additional type handling field and the six-bit opcode translation field are concatenated to form a single six-bit field, which specifies a scheme of six-bit opcode translation that may include additional types not reachable by untranslated seven-bit opcodes, and which also specifies a scheme of seven-bit opcode translation.
When the seven-bit translation mode bit is zero, if the three-bit additional type handling field in the Program Status Block contains 000, then seven-bit opcodes are not modified, but instead indicate the operations described in previous sections, as well as the three-bit six-bit opcode translation field indicating the standard translations for six-bit opcodes given above.
When the seven-bit translation mode bit is a one, the three-bit additional type handling field indicates how the opcodes normally used for floating-point operations are instead interpreted as acting on an additional data type.
When the three bits in the additional data type handling field have the value 000 while the seven-bit translation mode bit is a one, they specify that the register packed arithmetic instructions, normally created with the mode-independent prefix 170603, are available within the normal opcode range.
In this case, opcodes beginning with 1000 and 1001 are used for the register packed instructions; opcodes beginning with 1010 and 1011 are used for the register packed long instructions, and the remaining memory-reference instructions have their opcodes, exclusive of the leading zero bit, translated into seven-bit opcodes in the same fashion as indicated by the opcode translate field for other modes.
Thus, in this circumstance, the opcodes of the various register packed instructions are:
101xxx RPC Register Packed Compare 104xxx RPA Register Packed Add 105xxx RPS Register Packed Subtract 106xxx RPM Register Packed Multiply 107xxx RPD Register Packed Divide 116xxx RPME Register Packed Multiply Extensibly 117xxx RPDE Register Packed Divide Extensibly 121xxx RPCL Register Packed Compare Long 124xxx RPAL Register Packed Add Long 125xxx RPSL Register Packed Subtract Long 126xxx RPML Register Packed Multiply Long 127xxx RPDL Register Packed Divide Long 136xxx RPMEL Register Packed Multiply Extensibly Long 137xxx RPDEL Register Packed Divide Extensibly Long
When the three bits in the additional data type handling field have the value 001 while the seven-bit translation mode bit is a one, the compressed decimal register packed instructions are the ones which make use of the regular floating-point opcodes, with opcodes as follows:
121xxx RCDC Register Compressed Decimal Compare 122xxx RCDME Register Compressed Decimal Multiply Extensibly 123xxx RCDDE Register Compressed Decimal Divide Extensibly 124xxx RCDA Register Compressed Decimal Add 125xxx RCDS Register Compressed Decimal Subtract 126xxx RCDM Register Compressed Decimal Multiply 127xxx RCDD Register Compressed Decimal Divide 131xxx RCDCL Register Compressed Decimal Compare Long 132xxx RCDMEL Register Compressed Decimal Multiply Extensibly Long 133xxx RCDDEL Register Compressed Decimal Divide Extensibly Long 134xxx RCDAL Register Compressed Decimal Add Long 135xxx RCDSL Register Compressed Decimal Subtract Long 136xxx RCDML Register Compressed Decimal Multiply Long 137xxx RCDDL Register Compressed Decimal Divide Long
When the three bits in the additional data type handling field have the value 010 while the seven-bit translation mode bit is a one, it is the simple floating operations that are given the opcodes that begin with the two bits 10; those for the simple floating halfword type receive opcodes that start with 1001, those for the simple floating type receive opcodes that start with 1010, and those for the simple floating long type receive opcodes that start with 1011.
Again, the last six bits of a seven-bit opcode which begins with 0 are translated, as a six bit opcode, in accordance with the three bits in the six-bit opcode translation field of the Program Status Block.
The opcodes of the simple floating instructions in this circumstance are:
110xxx SFSWL Simple Floating Swap Halfword 111xxx SFCL Simple Floating Compare Halfword 112xxx SFLL Simple Floating Load Halfword 113xxx SFSTL Simple Floating Store Halfword 114xxx SFAL Simple Floating Add Halfword 115xxx SFSL Simple Floating Subtract Halfword 116xxx SFML Simple Floating Multiply Halfword 117xxx SFDL Simple Floating Divide Halfword 120xxx SFSW Simple Floating Swap 121xxx SFC Simple Floating Compare 122xxx SFL Simple Floating Load 123xxx SFST Simple Floating Store 124xxx SFA Simple Floating Add 125xxx SFS Simple Floating Subtract 126xxx SFM Simple Floating Multiply 127xxx SFD Simple Floating Divide 130xxx SFSWL Simple Floating Swap Long 131xxx SFCL Simple Floating Compare Long 132xxx SFLL Simple Floating Load Long 133xxx SFSTL Simple Floating Store Long 134xxx SFAL Simple Floating Add Long 135xxx SFSL Simple Floating Subtract Long 136xxx SFML Simple Floating Multiply Long 137xxx SFDL Simple Floating Divide Long
When the three bits in the additional data type handling field have the value 011 while the seven-bit translation mode bit is a one, the decimal exponent data types are the ones which are provided as the additional data type, and their opcodes are:
100xxx DESWM Decimal Exponent Swap Medium 101xxx DECM Decimal Exponent Compare Medium 102xxx DELM Decimal Exponent Load Medium 103xxx DESTM Decimal Exponent Store Medium 104xxx DEAM Decimal Exponent Add Medium 105xxx DESM Decimal Exponent Subtract Medium 106xxx DEMM Decimal Exponent Multiply Medium 107xxx DEDM Decimal Exponent Divide Medium 130xxx DESWL Decimal Exponent Swap Long 131xxx DECL Decimal Exponent Compare Long 132xxx DELL Decimal Exponent Load Long 133xxx DESTL Decimal Exponent Store Long 134xxx DEAL Decimal Exponent Add Long 135xxx DESL Decimal Exponent Subtract Long 136xxx DEML Decimal Exponent Multiply Long 137xxx DEDL Decimal Exponent Divide Long
When the seven-bit translation mode bit is a zero, as noted above, the additional type handling field and the six-bit opcode translation scheme instead act as a single six-bit field. This both allows schemes of six-bit opcode translation which allow access to additional types, and it allows schemes of seven-bit opcode translation which are not composed of a separate six-bit portion with the conventional types plus a supplement with an additional type.
This permits schemes of opcode translation to be defined where only some of the register packed types, or only some of the simple floating types, are available, so that more of the conventional types will be available, or schemes of opcode translation in which both some or all of the register packed types and some or all of the simple floating types are available.
The table below shows the different translation schemes that can be specified for seven-bit opcodes, and the translation scheme that is in effect for six-bit opcodes for the same values of these bits:
Contents of Opcode Translation Fields
0 001 000 0 001 001 0 001 010 0 001 011
(seven-bit opcodes)
0000 0000 Byte 0000 Byte 0000 Byte 0000 Byte
0001 0001 0001 0001 0001
0010 0010 Halfword 0010 Halfword 0010 Halfword 0010 Halfword
0011 0011 0011 0011 0011
0100 0100 Integer 0100 Integer 0100 Integer 0100 Integer
0101 0101 0101 0101 0101
0110 0110 Long 0110 Long SF RP Long
0111 0111 0111 SF Long (ext)
1000 1001 Floating 1001 Floating 1000 Medium 1000 Medium
1001 1011 Double 1011 Double 1001 Floating 1001 Floating
1010 SF RP Long 1010 Double 1010 Double
1011 SF Long (ext) 1011 Quad 1011 Quad
(six-bit opcodes)
000 0000 Byte 0010 Halfword 0010 Halfword 0010 Halfword
001 0001 0011 0011 0011
010 0010 Halfword 0100 Integer 0100 Integer 0100 Integer
011 0011 0101 0101 0101
100 0110 Long 0110 Long SF RP Long
101 0111 0111 SF Long (ext)
110 SF RP Long 1001 Floating 1010 Double
111 SF Long (ext) 1010 Double 1011 Quad
Contents of Opcode Translation Fields
0 001 100 0 001 101 0 001 110 0 001 111
(seven-bit opcodes)
0000 0000 Byte 0010 Halfword 0000 Byte 0000 Byte
0001 0001 0011 0010 Halfword 0001
0010 0010 Halfword 0100 Integer 0100 Integer 0010 Halfword
0011 0011 0101 0110 Long 0011
0100 0100 Integer 1001 Floating 1000 Medium 0100 Integer
0101 0101 1010 Double 1001 Floating 0101
0110 1001 Floating SF 1010 Double SF
0111 1010 Double SF Long 1011 Quad SF Long
1000 SF RP RP Long RP
1001 SF Long (ext) SF Halfword (ext)
1010 RP Long RP Long SF RP Long
1011 (ext) (ext) SF Long (ext)
Contents of Opcode Translation Fields
0 010 000 0 010 001 0 010 010 0 010 011
(seven-bit opcodes)
0000 0000 Byte 0000 Byte 0000 Byte 0000 Byte
0001 0001 0001 0001 0001
0010 0010 Halfword 0010 Halfword 0010 Halfword 0010 Halfword
0011 0011 0011 0011 0011
0100 0100 Integer 0100 Integer 0100 Integer 0100 Integer
0101 0101 0101 0101 0101
0110 0110 Long 0110 Long 0110 Long 0110 Long
0111 0111 0111 0111 0111
1100 1001 Floating 1010 Double Reg Pack CD Reg Pack
1101 (unnormalized) (unnormalized) Reg Pack Long CD Reg Pack L
1110 1010 Double 1011 Quad 1001 Floating 1001 Floating
1111 (unnormalized) (unnormalized) 1010 Double 1010 Double
(six-bit opcodes)
000 0010 Halfword 0010 Halfword 0010 Halfword 0010 Halfword
001 0011 0011 0011 0011
010 0100 Integer 0100 Integer 0100 Integer 0100 Integer
011 0101 0101 0101 0101
100 1001 Floating 1010 Double Reg Pack CD Reg Pack
101 (unnormalized) (unnormalized) Reg Pack Long CD Reg Pack L
110 1010 Double 1011 Quad 1001 Floating 1001 Floating
111 (unnormalized) (unnormalized) 1010 Double 1010 Double
Contents of Opcode Translation Fields
0 010 100 0 001 101 0 001 110 0 001 111
(six-bit opcodes)
000 0010 Halfword 0010 Halfword 0000 Byte 0000 Byte
001 0011 0011 0001 0001
010 0100 Integer 0100 Integer 0010 Halfword 0010 Halfword
011 0101 0101 0011 0011
100 Dec Exp Med Reg Pack 0100 Integer 0100 Integer
110 Dec Exp Long Reg Pack Long 0101 0101
110 1001 Floating Dec Exp Med Reg Pack CD Reg Pack
111 1010 Double Dec Exp Long Reg Pack Long CD Reg Pack L
Note that, at this time, not all the possible combinations have been given defined meanings.