In this mode, the two sets of sixty-four supplementary registers are used as two stacks with sixty-four elements each. The normal eight arithmetic-index registers and the eight floating-point registers are not used, except that the stack pointers for these two stacks may be kept in the arithmetic-index registers, and, as well, they may contain both a pointer for a stack of subroutine return addresses, and the bounds of the area in memory used for that stack. The base registers have their usual function, except that base register 0 is also used as a base register. The scratchpad registers, the pointer scratchpad registers, and the array scratchpad registers combine to form one set of eight compound pointer registers, in which the scratchpad register holds a limit value, the pointer scratchpad register holds an increment value, and the array scratchpad register holds the pointer to memory.
This mode is strongly inspired by the English Electric KDF 9 computer, as may particularly be inferred from the compound pointer registers, which closely resemble that machine's Q-store; however, the need to specify a base register in the push and pop instructions limits the number of possible instructions available compared to that machine, and the fact that memory, instead of register space, is used for the subroutine return stack is another important difference.
Note also that since this mode uses the normal eight base registers used in conventional modes of operation, unlike the other variant alignment modes, direct cache mode may be used with this mode of operation, in which either the first four base registers are used, or the memory address in the instruction is an 18-bit address pointing to an area in cache.
The following diagram shows the format of instructions in this mode:
The first line shows the format of the push and pop instructions:
00000xxx PSB Push Byte 01000xxx PPB Pop Byte 00001xxx PSH Push Halfword 01001xxx PPH Pop Halfword 00010xxx PS Push 01010xxx PP Pop 00011xxx PSL Push Long 01011xxx PPL Pop Long 00000xxx PSM Push Medium 01000xxx PPM Pop Medium 00001xxx PSF Push Floating 01001xxx PPF Pop Floating 00010xxx PSD Push Double 01010xxx PPD Pop Double 00011xxx PSQ Push Quad 01011xxx PPQ Pop Quad
The byte, halfword, word, and long push and pop instructions transfer data between the supplementary arithmetic-index registers and memory, and the medium, floating, double, and quad push and pop instructions transfer data between the supplementary floating-point registers and memory.
The second line shows the format of arithmetic operations. The available opcodes are:
10000 AU Add Unnormalized 10001 X XOR SU Subtract Unnormalized 10010 N And MU Multiply Unnormalized 10011 O Or DU Divide Unnormalized 10100 A Add 10101 S Subtract 10110 M Multiply 10111 D Divide
where, for the first four opcodes, the first column shows the operation for a fixed-point type, the second for a floating-point type. The type suffixes follow the usual conventions, but are not shown.
The third line shows the format for jump instructions, of which there are two:
11000 JMP Jump 11001 JSR Jump to Subroutine
Both branch to the instruction at the effective address; the JSR instruction pushes the return address, that of the instruction which follows it, on the subroutine return stack.
The fourth line shows the format for stack manipulation operations. These only require one bit to indicate the type, to show which stack is to be manipulated.
11010000 DUP Duplicate 11010010 DROP 11010100 SWAP 11010110 ROT Rotate 11010001 DUPF Duplicate Floating 11010011 DROPF Drop Floating 11010101 SWAPF Swap Floating 11010111 ROTF Rotate Floating
The actions of these instructions are:
The fifth line shows the formats of stack manipulation instructions that require a parameter:
11011000 RETR Retrieve 11011001 RETRF Retrieve Floating
The parameter byte for the Retrieve instruction may contain a number from 0 through 63, with 0 referring to the top of the stack, and successive numbers referring to items deeper in the stack, and the instruction takes that item, and pushes a copy of that item on the top of the stack.
The sixth line shows miscellaneous operations that do not have a type associated with them.
The seventh line shows the format of the branch instructions.
11101000 BSR Branch to Subroutine 11101001 BLT Branch if Less Than 11101010 BEQ Branch if Equal 11101011 BLE Branch if Less Than or Equal 11101100 BGT Branch if Greater Than 11101101 BNE Branch if Not Equal 11101110 BGE Branch if Greater Than or Equal 11101111 BRA Branch
The eighth line shows operations used to work with arrays in memory, as well as operations to access the pointer registers which allow memory arrays to be accessed.
00000 PSA Push from Array 00001 PPA Pop to Array 00100 PSAA Push from Array and Advance 00101 PPAA Pop to Array and Advance 00110 PSAR Push from Array and Retreat 00111 PPAR Pop to Array and Retreat
In these operations, which access the pointer registers, the type field is not used, and must be zero:
11000 PPPL Pop to Pointer Limit 11001 PPPI Pop to Pointer Increment 11010 PPP Pop to Pointer 11100 PSPL Push from Pointer Limit 11101 PSPI Push from Pointer Increment 11110 PSP Push from Pointer
And in this operation, the type field is used, but the pointer register field is not used and must be zero:
11111 PI Push Immediate
This opcode is followed by an immediate value, occupying as many bytes as is necessary.
The ninth line shows the one-address floating-point operations. In these, only two bits are required to specify one of the four floating-point types.
00000000 SIN Sine 00000001 COS Cosine 00000010 TAN Tangent 00000100 ASN Arcsine 00000101 ACS Arccosine 00000110 ATN Arctangent 00001000 SINH Hyperbolic Sine 00001001 COSH Hyperbolic Cosine 00001010 TANH Hyperbolic Tangent 00001100 ASNH Inverse Hyperbolic Sine 00001101 ACSH Inverse Hyperbolic Cosine 00001110 ATNH Inverse Hyperbolic Tangent 00010000 SQR Square Root 00010001 QBR Cube Root 00010010 LOG Logarithm 00010011 EXP Exponential 00010100 ABS Absolute Value 00010101 SGN Signum 00010110 NEG Negate
Once again, the type suffixes follow the usual conventions, but are not shown.
Finally, the following instructions also take a one-byte parameter, like the conditional branch instructions, but do not have a line in the diagram above:
11111100 SETAM Set Addressing Mode 11111101 INWM Interpret Next With Mode
and they allow switching to the other instruction modes on the computer.