As is obvious from the diagram below illustrating the instruction format for this mode, it is patterned after that of the Digital Equipment Corporation's VAX computer:
but it does have some important differences as well.
The most major one is that fewer addressing modes are offered; instead, more registers can be specified by the instruction; instead of sixteen registers, one of sixty-four scratchpad registers are used as operands or as index registers, and one of thirty-two base registers are used in memory-reference instructions.
A second one is that because this architecture does not include either a length field or a terminating character in its native string and packed decimal data types, a length field is an additional optional instruction element immediately following the eight-bit opcode. Also, a 16-bit length field is uses as another optional instruction element in vector instructions.
As with the VAX, the number of operands of an instruction are determined by the opcode, and all instructions have the same format.
Bytes of the form 11xxxxxx prefix an operand field to indicate indexing; as well, a byte of the form 10xxxxxx indicates indexing by an index register that is incremented after use.
Scratchpad register 0 cannot be used as an index; the byte 11000000 can be used as a dummy index prefix byte. This is applicable only to indirect addressing; if an operand field indicating indirect addressing is preceded by one index byte, this indicates pre-indirect indexing; if by two, the second index byte provides an index register used for post-indirect indexing. If only post-indirect indexing is desired, the dummy index prefix byte is used.
A byte of the form 00ssssss indicates an operand that is one of the scratchpad registers, whether arithmetic/index or floating-point depends on the type of the instruction.
A byte of the form 010bbbbb specifies a base register, from the same set of 32 base registers used in Vector Register Mode, and is followed by a 16-bit address (unless these addresses are increased to 32 bits in size by the 32/28-bit addressing bit of the Program Status Block), and the address is added to the contents of the specified base register to form the effective address.
Base register 0 cannot be used as a base register, and thus the byte 01000000 instead precedes an immediate operand, of the length indicated by the type of the instruction.
A byte of the form 011bbbbb also specifies a base register, and the 16-bit address added to it forms a pointer to a 32-bit value in memory (or a 64-bit value, if 64-bit addressing is indicated in the Program Status Block) which serves as the actual effective address of the instruction; thus, this indicates indirect addressing.
The opcodes of the most important instructions used in this mode are:
00 oD oS SWB Swap Byte 01 oD oS CB Compare Byte 02 oD oS MVB Move Byte 04 oD oS AB Add Byte 05 oD oS SB Subtract Byte 08 oD oS IB Insert Byte 09 oD oS UCB Unsigned Compare Byte 0A oD oS ULB Unsigned Load Byte 0B oD oS XB XOR Byte 0C oD oS NB AND Byte 0D oD oS OB OR Byte 0F oD oS STGB Store if Greater Byte 10 oD oS SWH Swap Halfword 11 oD oS CH Compare Halfword 12 oD oS MVH Move Halfword 14 oD oS AH Add Halfword 15 oD oS SH Subtract Halfword 16 oD oS MH Multiply Halfword 17 oD oS DH Divide Halfword 18 oD oS IH Insert Halfword 19 oD oS UCH Unsigned Compare Halfword 1A oD oS ULH Unsigned Load Halfword 1B oD oS XH XOR Halfword 1C oD oS NH AND Halfword 1D oD oS OH OR Halfword 1E oD oS MEH Multiply Extensibly Halfword 1F oD oS DEH Divide Extensibly Halfword 20 oD oS SW Swap 21 oD oS C Compare 22 oD oS MV Move 24 oD oS A Add 25 oD oS S Subtract 26 oD oS M Multiply 27 oD oS D Divide 28 oD oS I Insert 29 oD oS UC Unsigned Compare 2A oD oS UL Unsigned Load 2B oD oS X XOR 2C oD oS N AND 2D oD oS O OR 2E oD oS ME Multiply Extensibly 2F oD oS DE Divide Extensibly 30 oD oS SWL Swap Long 31 oD oS CL Compare Long 32 oD oS MVL Move Long 34 oD oS AL Add Long 35 oD oS SL Subtract Long 36 oD oS ML Multiply Long 37 oD oS DL Divide Long 39 oD oS UCL Unsigned Compare Long 3B oD oS XL XOR Long 3C oD oS NL AND Long 3D oD oS OL OR Long 3E oD oS MEL Multiply Extensibly Long 3F oD oS DEL Divide Extensibly Long 40 oD oS SWM Swap Medium 41 oD oS CM Compare Medium 42 oD oS MVM Move Medium 44 oD oS AM Add Medium 45 oD oS SM Subtract Medium 46 oD oS MM Multiply Medium 47 oD oS DM Divide Medium 48 oD oS SWF Swap Floating 49 oD oS CF Compare Floating 4A oD oS MVF Move Floating 4C oD oS AF Add Floating 4D oD oS SF Subtract Floating 4E oD oS MF Multiply Floating 4F oD oS DF Divide Floating 50 oD oS SWD Swap Double 51 oD oS CD Compare Double 52 oD oS MVD Move Double 54 oD oS AD Add Double 55 oD oS SD Subtract Double 56 oD oS MD Multiply Double 57 oD oS DD Divide Double 58 oD oS SWQ Swap Quad 59 oD oS CQ Compare Quad 5A oD oS MVQ Move Quad 5C oD oS AQ Add Quad 5D oD oS SQ Subtract Quad 5E oD oS MQ Multiply Quad 5F oD oS DQ Divide Quad 6000 pL oD oS MESTP Multiply Extensibly and Store Packed 6001 pL oD oS CP Compare Packed 6002 pL oD oS MVP Move Packed 6003 pL oR oQ oO oS DSTRP Divide and Store Remainder Packed 6004 pL oD oS AP Add Packed 6005 pL oD oS SP Subtract Packed 6006 pL oD oS MP Multiply Packed 6007 pL oD oS DP Divide Packed 6012 sL oD oS MVC Move Character 6015 sL oD oS CC Compare Character 6016 sL oD oS P Pack 6017 sL oD oS U Unpack 601A sL oD oS MVCH Move Halfword Characters 601D sL oD oS CCH Compare Halfword Characters 601E sL oD oS PH Pack Halfword 601F sL oD oS UH Unpack Halfword 6020 sL oD oS CVPB Convert Packed to Byte 6021 sL oD oS CVPH Convert Packed to Halfword 6022 sL oD oS CVPW Convert Packed to Word 6023 sL oD oS CVPL Convert Packed to Long 6024 sL oD oE oS CVPM Convert Packed to Medium 6025 sL oD oE oS CVPF Convert Packed to Floating 6026 sL oD oE oS CVPD Convert Packed to Double 6027 sL oD oE oS CVPQ Convert Packed to Quad 6028 sL oD oS CVBP Convert Byte to Packed 6029 sL oD oS CVHP Convert Halfword to Packed 602A sL oD oS CVWP Convert Word to Packed 602B sL oD oS CVLP Convert Long to Packed 602C sL oD oE oS CVMP Convert Medium to Packed 602D sL oD oE oS CVFP Convert Floating to Packed 602E sL oD oE oS CVDP Convert Double to Packed 602F sL oD oE oS CVQP Convert Quad to Packed 6030 sL vL oT oD oS CV Convert 6031 sL vL oT oD oS CVR Convert Reversed 6033 sL vL oT oD oS CVRI Convert Reversed Incomplete 6038 sL vL oT oD oS DCV Displaced Convert 6039 sL vL oT oD oS DCVR Displaced Convert Reversed 603B sL vL oT oD oS DCVRI Displaced Convert Reversed Incomplete 6040 sL oT oD oS TBH Translate Byte to Halfword 6041 sL oT oD oS TTHB Table Translate Halfword to Byte 6042 sL oT oD oS T Translate 6044 sL oT oD oS FMT Format 6045 sL oT oD oS SC Scan 604A sL oT oD oS TH Translate Halfword 604C sL oT oD oS FMTH Format Halfword 604D sL oT oD oS SCH Scan Halfword 6052 oD oS LBA Load Base Register 6053 oD oS SBA Store Base Register 6060 oR oJ JMS Jump to Subroutine 6071 oJ JL Jump if Low 6072 oJ JE Jump if Equal 6073 oJ JLE Jump if Low or Equal 6074 oJ JH Jump if High 6075 oJ JNE Jump if Not Equal 6076 oJ JHE Jump if High or Equal 6077 oJ JNV Jump if No Overflow 6078 oJ JV Jump if Overflow 607A oJ JC Jump if Carry 607B oJ JNC Jump if No Carry 607F oJ JMP Jump 6081 oR oJ RL Return if Low 6082 oR oJ RE Return if Equal 6083 oR oJ RLE Return if Low or Equal 6084 oR oJ RH Return if High 6085 oR oJ RNE Return if Not Equal 6086 oR oJ RHE Return if High or Equal 6087 oR oJ RNV Return if No Overflow 6088 oR oJ RV Return if Overflow 608A oR oJ RC Return if Carry 608B oR oJ RNC Return if No Carry 608F oR oJ RMP Return 60A0 oD CLRB Clear Byte 60A1 oD ABSB Absolute Value Byte 60A2 oD INVB Invert Byte 60A3 oD NEGB Negate Byte 60A4 oD oS NB Normalize Byte 60A8 oD CLRH Clear Halfword 60A9 oD ABSH Absolute Value Halfword 60AA oD INVH Invert Halfword 60AB oD NEGH Negate Halfword 60AC oD oS NH Normalize Halfword 60B0 oD CLR Clear 60B1 oD ABS Absolute Value 60B2 oD INV Invert 60B3 oD NEG Negate 60B4 oD oS N Normalize 60B8 oD CLRL Clear Long 60B9 oD ABSL Absolute Value Long 60BA oD INVL Invert Long 60BB oD NEGL Negate Long 60BC oD oS NL Normalize Long 60C0 sL oD SHLB Shift Left Byte 60C1 sL oD SHRB Shift Right Byte 60C3 sL oD ASRB Arithmetic Shift Right Byte 60C4 sL oD ROLB Rotate Left Byte 60C5 sL oD RORB Rotate Right Byte 60C6 sL oD RLCB Rotate Left through Carry Byte 60C7 sL oD RRCB Rotate Right through Carry Byte 60C8 sL oD SHLH Shift Left Halfword 60C9 sL oD SHRH Shift Right Halfword 60CB sL oD ASRH Arithmetic Shift Right Halfword 60CC sL oD ROLH Rotate Left Halfword 60CD sL oD RORH Rotate Right Halfword 60CE sL oD RLCH Rotate Left through Carry Halfword 60CF sL oD RRCH Rotate Right through Carry Halfword 60D0 sL oD SHL Shift Left 60D1 sL oD SHR Shift Right 60D3 sL oD ASR Arithmetic Shift Right 60D4 sL oD ROL Rotate Left 60D5 sL oD ROR Rotate Right 60D6 sL oD RLC Rotate Left through Carry 60D7 sL oD RRC Rotate Right through Carry 60D8 sL oD SHLL Shift Left Long 60D9 sL oD SHRL Shift Right Long 60DB sL oD ASRL Arithmetic Shift Right Long 60DC sL oD ROLL Rotate Left Long 60DD sL oD RORL Rotate Right Long 60DE sL oD RLCL Rotate Left through Carry Long 60DF sL oD RRCL Rotate Right through Carry Long 60E0 sL oD SEBI Separate Bits 60E5 oM oD oS BMM16 Bit-Matrix Multiply 16 60E6 oM oD oS BMM32 Bit-Matrix Multiply 32 60E7 oM oD oS BMM64 Bit-Matrix Multiply 64 60E9 oM1 oM2 oD oS BMSP16 Bit-Matrix Sum of Products 16 60EA oM1 oM2 oD oS BMSP32 Bit-Matrix Sum of Products 32 60EB oM1 oM2 oD oS BMSP64 Bit-Matrix Sum of Products 64 60ED oM oS LBMM16 Load Bit-Matrix Multiply 16 60EE oM oS LBMM32 Load Bit-Matrix Multiply 32 60EF oM oS LBMM64 Load Bit-Matrix Multiply 64 60F0 sL SETAM Set Addressing Mode 60F1 sL INWM Interpret Next With Mode 60F8 sL SVC Supervisor Call 6100 vL oD oS VSWB Vector Swap Byte 6101 vL oD oS VCB Vector Compare Byte 6102 vL oD oS VMVB Vector Move Byte 6108 vL oD oS VIB Vector Insert Byte 6109 vL oD oS VUCB Vector Unsigned Compare Byte 610A vL oD oS VULB Vector Unsigned Load Byte 6110 vL oD oS VSWH Vector Swap Halfword 6111 vL oD oS VCH Vector Compare Halfword 6112 vL oD oS VMVH Vector Move Halfword 6118 vL oD oS VIH Vector Insert Halfword 6119 vL oD oS VUCH Vector Unsigned Compare Halfword 611A vL oD oS VULH Vector Unsigned Load Halfword 6120 vL oD oS VSW Vector Swap 6121 vL oD oS VC Vector Compare 6122 vL oD oS VMV Vector Move 6128 vL oD oS VI Vector Insert 6129 vL oD oS VUC Vector Unsigned Compare 612A vL oD oS VUL Vector Unsigned Load 6130 vL oD oS VSWL Vector Swap Long 6131 vL oD oS VCL Vector Compare Long 6132 vL oD oS VMVL Vector Move Long 6139 vL oD oS VUCL Vector Unsigned Compare Long 6140 vL oD oS VSWM Vector Swap Medium 6141 vL oD oS VCM Vector Compare Medium 6142 vL oD oS VMVM Vector Move Medium 6148 vL oD oS VSWF Vector Swap Floating 6149 vL oD oS VCF Vector Compare Floating 614A vL oD oS VMVF Vector Move Floating 6150 vL oD oS VSWD Vector Swap Double 6151 vL oD oS VCD Vector Compare Double 6152 vL oD oS VMVD Vector Move Double 6158 vL oD oS VSWQ Vector Swap Quad 6159 vL oD oS VCQ Vector Compare Quad 615A vL oD oS VMVQ Vector Move Quad 6400 oD SINM Sine Medium 6401 oD COSM Cosine Medium 6402 oD TANM Tangent Medium 6404 oD ASNM Arcsine Medium 6405 oD ACSM Arccosine Medium 6406 oD ATNM Arctangent Medium 6408 oD SINHM Hyperbolic Sine Medium 6409 oD COSHM Hyperbolic Cosine Medium 640A oD TANHM Hyperbolic Tangent Medium 640C oD ASNHM Inverse Hyperbolic Sine Medium 640D oD ACSHM Inverse Hyperbolic Cosine Medium 640E oD ATNHM Inverse Hyperbolic Tangent Medium 6410 oD SQRM Square Root Medium 6411 oD QBRM Cube Root Medium 6412 oD LOGM Logarithm Medium 6413 oD EXPM Exponential Medium 6414 oD CLRM Clear Medium 6415 oD ABSM Absolute Value Medium 6416 oD SGNM Signum Medium 6417 oD NEGM Negate Medium 6420 oD SINF Sine Floating 6421 oD COSF Cosine Floating 6422 oD TANF Tangent Floating 6424 oD ASNF Arcsine Floating 6425 oD ACSF Arccosine Floating 6426 oD ATNF Arctangent Floating 6428 oD SINHF Hyperbolic Sine Floating 6429 oD COSHF Hyperbolic Cosine Floating 642A oD TANHF Hyperbolic Tangent Floating 642C oD ASNHF Inverse Hyperbolic Sine Floating 642D oD ACSHF Inverse Hyperbolic Cosine Floating 642E oD ATNHF Inverse Hyperbolic Tangent Floating 6430 oD SQRF Square Root Floating 6431 oD QBRF Cube Root Floating 6432 oD LOGF Logarithm Floating 6433 oD EXPF Exponential Floating 6434 oD CLRF Clear Floating 6435 oD ABSF Absolute Value Floating 6436 oD SGNF Signum Floating 6437 oD NEGF Negate Floating 6440 oD SIND Sine Double 6441 oD COSD Cosine Double 6442 oD TAND Tangent Double 6444 oD ASND Arcsine Double 6445 oD ACSD Arccosine Double 6446 oD ATND Arctangent Double 6448 oD SINHD Hyperbolic Sine Double 6449 oD COSHD Hyperbolic Cosine Double 644A oD TANHD Hyperbolic Tangent Double 644C oD ASNHD Inverse Hyperbolic Sine Double 644D oD ACSHD Inverse Hyperbolic Cosine Double 644E oD ATNHD Inverse Hyperbolic Tangent Double 6450 oD SQRD Square Root Double 6451 oD QBRD Cube Root Double 6452 oD LOGD Logarithm Double 6453 oD EXPD Exponential Double 6454 oD CLRD Clear Double 6455 oD ABSD Absolute Value Double 6456 oD SGND Signum Double 6457 oD NEGD Negate Double 6460 oD SINQ Sine Quad 6461 oD COSQ Cosine Quad 6462 oD TANQ Tangent Quad 6464 oD ASNQ Arcsine Quad 6465 oD ACSQ Arccosine Quad 6466 oD ATNQ Arctangent Quad 6468 oD SINHQ Hyperbolic Sine Quad 6469 oD COSHQ Hyperbolic Cosine Quad 646A oD TANHQ Hyperbolic Tangent Quad 646C oD ASNHQ Inverse Hyperbolic Sine Quad 646D oD ACSHQ Inverse Hyperbolic Cosine Quad 646E oD ATNHQ Inverse Hyperbolic Tangent Quad 6470 oD SQRQ Square Root Quad 6471 oD QBRQ Cube Root Quad 6472 oD LOGQ Logarithm Quad 6473 oD EXPQ Exponential Quad 6474 oD CLRQ Clear Quad 6475 oD ABSQ Absolute Value Quad 6476 oD SGNQ Signum Quad 6477 oD NEGQ Negate Quad 6482 oD oS LMB Load Medium with Byte 6483 oD oS STMB Store Medium in Byte 6484 oD oS AMB Add Byte to Medium 6485 oD oS SMB Subtract Byte from Medium 6486 oD oS MMB Multiply Medium by Byte 6487 oD oS DMB Divide Medium by Byte 648A oD oS LMH Load Medium with Halfword 648B oD oS STMH Store Medium in Halfword 648C oD oS AMH Add Halfword to Medium 648D oD oS SMH Subtract Halfword from Medium 648E oD oS MMH Multiply Medium by Halfword 648F oD oS DMH Divide Medium by Halfword 6492 oD oS LMI Load Medium with Integer 6493 oD oS STMI Store Medium in Integer 6494 oD oS AMI Add Integer to Medium 6495 oD oS SMI Subtract Integer from Medium 6496 oD oS MMI Multiply Medium by Integer 6497 oD oS DMI Divide Medium by Integer 649A oD oS LML Load Medium with Long 649B oD oS STML Store Medium in Long 649C oD oS AML Add Long to Medium 649D oD oS SML Subtract Long from Medium 649E oD oS MML Multiply Medium by Long 649F oD oS DML Divide Medium by Long 64A2 oD oS LFB Load Floating with Byte 64A3 oD oS STFB Store Floating in Byte 64A4 oD oS AFB Add Byte to Floating 64A5 oD oS SFB Subtract Byte from Floating 64A6 oD oS MFB Multiply Floating by Byte 64A7 oD oS DFB Divide Floating by Byte 64AA oD oS LFH Load Floating with Halfword 64AB oD oS STFH Store Floating in Halfword 64AC oD oS AFH Add Halfword to Floating 64AD oD oS SFH Subtract Halfword from Floating 64AE oD oS MFH Multiply Floating by Halfword 64AF oD oS DFH Divide Floating by Halfword 64B2 oD oS LFI Load Floating with Integer 64B3 oD oS STFI Store Floating in Integer 64B4 oD oS AFI Add Integer to Floating 64B5 oD oS SFI Subtract Integer from Floating 64B6 oD oS MFI Multiply Floating by Integer 64B7 oD oS DFI Divide Floating by Integer 64BA oD oS LFL Load Floating with Long 64BB oD oS STFL Store Floating in Long 64BC oD oS AFL Add Long to Floating 64BD oD oS SFL Subtract Long from Floating 64BE oD oS MFL Multiply Floating by Long 64BF oD oS DFL Divide Floating by Long 64C2 oD oS LDB Load Double with Byte 64C3 oD oS STDB Store Double in Byte 64C4 oD oS ADB Add Byte to Double 64C5 oD oS SDB Subtract Byte from Double 64C6 oD oS MDB Multiply Double by Byte 64C7 oD oS DDB Divide Double by Byte 64CA oD oS LDH Load Double with Halfword 64CB oD oS STDH Store Double in Halfword 64CC oD oS ADH Add Halfword to Double 64CD oD oS SDH Subtract Halfword from Double 64CE oD oS MDH Multiply Double by Halfword 64CF oD oS DDH Divide Double by Halfword 64D2 oD oS LDI Load Double with Integer 64D3 oD oS STDI Store Double in Integer 64D4 oD oS ADI Add Integer to Double 64D5 oD oS SDI Subtract Integer from Double 64D6 oD oS MDI Multiply Double by Integer 64D7 oD oS DDI Divide Double by Integer 64DA oD oS LDL Load Double with Long 64DB oD oS STDL Store Double in Long 64DC oD oS ADL Add Long to Double 64DD oD oS SDL Subtract Long from Double 64DE oD oS MDL Multiply Double by Long 64DF oD oS DDL Divide Double by Long 64E2 oD oS LQB Load Quad with Byte 64E3 oD oS STQB Store Quad in Byte 64E4 oD oS AQB Add Byte to Quad 64E5 oD oS SQB Subtract Byte from Quad 64E6 oD oS MQB Multiply Quad by Byte 64E7 oD oS DQB Divide Quad by Byte 64EA oD oS LQH Load Quad with Halfword 64EB oD oS STQH Store Quad in Halfword 64EC oD oS AQH Add Halfword to Quad 64ED oD oS SQH Subtract Halfword from Quad 64EE oD oS MQH Multiply Quad by Halfword 64EF oD oS DQH Divide Quad by Halfword 64F2 oD oS LQI Load Quad with Integer 64F3 oD oS STQI Store Quad in Integer 64F4 oD oS AQI Add Integer to Quad 64F5 oD oS SQI Subtract Integer from Quad 64F6 oD oS MQI Multiply Quad by Integer 64F7 oD oS DQI Divide Quad by Integer 64FA oD oS LQL Load Quad with Long 64FB oD oS STQL Store Quad in Long 64FC oD oS AQL Add Long to Quad 64FD oD oS SQL Subtract Long from Quad 64FE oD oS MQL Multiply Quad by Long 64FF oD oS DQL Divide Quad by Long 6600 oM oD oS SWBSV Swap Byte Short Vector 6602 oM oD oS MVBSV Move Byte Short Vector 6604 oM oD oS ABSV Add Byte Short Vector 6605 oM oD oS SBSV Subtract Byte Short Vector 6608 oM oD oS SMBPB Set Mask Bit if Positive Byte 6609 oM oD oS SMBZB Set Mask Bit if Zero Byte 660A oM oD oS SMBNB Set Mask Bit if Negative Byte 660D oM oD oS XBSV XOR Byte Short Vector 660E oM oD oS NBSV AND Byte Short Vector 660F oM oD oS OBSV OR Byte Short Vector 6610 oM oD oS SWHSV Swap Halfword Short Vector 6612 oM oD oS MVHSV Move Halfword Short Vector 6614 oM oD oS AHSV Add Halfword Short Vector 6615 oM oD oS SHSV Subtract Halfword Short Vector 6616 oM oD oS MHSV Multiply Halfword Short Vector 6617 oM oD oS DHSV Divide Halfword Short Vector 6618 oM oD oS SMBPH Set Mask Bit if Positive Halfword 6619 oM oD oS SMBZH Set Mask Bit if Zero Halfword 661A oM oD oS SMBNH Set Mask Bit if Negative Halfword 661D oM oD oS XHSV XOR Halfword Short Vector 661E oM oD oS NHSV AND Halfword Short Vector 661F oM oD oS OHSV OR Halfword Short Vector 6620 oM oD oS SWSV Swap Short Vector 6622 oM oD oS MVSV Move Short Vector 6624 oM oD oS ASV Add Short Vector 6625 oM oD oS SSV Subtract Short Vector 6626 oM oD oS MSV Multiply Short Vector 6627 oM oD oS DSV Divide Short Vector 6628 oM oD oS SMBP Set Mask Bit if Positive 6629 oM oD oS SMBZ Set Mask Bit if Zero 662A oM oD oS SMBN Set Mask Bit if Negative 662D oM oD oS XSV XOR Short Vector 662E oM oD oS NSV AND Short Vector 662F oM oD oS OSV OR Short Vector 6630 oM oD oS SWLSV Swap Long Short Vector 6632 oM oD oS MVLSV Move Long Short Vector 6634 oM oD oS ALSV Add Long Short Vector 6635 oM oD oS SLSV Subtract Long Short Vector 6636 oM oD oS MLSV Multiply Long Short Vector 6637 oM oD oS DLSV Divide Long Short Vector 6638 oM oD oS SMBPL Set Mask Bit if Positive Long 6639 oM oD oS SMBZL Set Mask Bit if Zero Long 663A oM oD oS SMBNL Set Mask Bit if Negative Long 663D oM oD oS XLSV XOR Long Short Vector 663E oM oD oS NLSV AND Long Short Vector 663F oM oD oS OLSV OR Long Short Vector 6642 oM oD oS MVSMSV Move Small Short Vector 6644 oM oD oS ASMSV Add Small Short Vector 6645 oM oD oS SSMSV Subtract Small Short Vector 6646 oM oD oS MSMSV Multiply Small Short Vector 6647 oM oD oS DSMSV Divide Small Short Vector 6648 oM oD oS SMBPSM Set Mask Bit if Positive Small 6649 oM oD oS SMBZSM Set Mask Bit if Zero Small 664A oM oD oS SMBNSM Set Mask Bit if Negative Small 664E oD oS SHSMHSV Shuffle Small/Halfword Short Vector 6652 oM oD oS MVFSV Move Floating Short Vector 6654 oM oD oS AFSV Add Floating Short Vector 6655 oM oD oS SFSV Subtract Floating Short Vector 6656 oM oD oS MFSV Multiply Floating Short Vector 6657 oM oD oS DFSV Divide Floating Short Vector 6658 oM oD oS SMBPF Set Mask Bit if Positive Floating 6659 oM oD oS SMBZF Set Mask Bit if Zero Floating 665A oM oD oS SMBNF Set Mask Bit if Negative Floating 665E oD oS SHFWSV Shuffle Floating/Word Short Vector 6662 oM oD oS MVDSV Move Double Short Vector 6664 oM oD oS ADSV Add Double Short Vector 6665 oM oD oS SDSV Subtract Double Short Vector 6666 oM oD oS MDSV Multiply Double Short Vector 6667 oM oD oS DDSV Divide Double Short Vector 6668 oM oD oS SMBPD Set Mask Bit if Positive Double 6669 oM oD oS SMBZD Set Mask Bit if Zero Double 666A oM oD oS SMBND Set Mask Bit if Negative Double 666E oD oS SHDLSV Shuffle Double/Long Short Vector 6670 oM oD oS SWQSV Swap Quad Short Vector 6672 oM oD oS MVQSV Move Quad Short Vector 6674 oM oD oS AQSV Add Quad Short Vector 6675 oM oD oS SQSV Subtract Quad Short Vector 6676 oM oD oS MQSV Multiply Quad Short Vector 6677 oM oD oS DQSV Divide Quad Short Vector 6678 oM oD oS SMBPQ Set Mask Bit if Positive Quad 6679 oM oD oS SMBZQ Set Mask Bit if Zero Quad 667A oM oD oS SMBNQ Set Mask Bit if Negative Quad 667E oD oS SHQSV Shuffle Quad Short Vector 84 oD oO oS ABT Add Byte Three-Address 85 oD oO oS SBT Subtract Byte Three-Address 8B oD oO oS XBT XOR Byte Three-Address 8C oD oO oS NBT AND Byte Three-Address 8D oD oO oS OBT OR Byte Three-Address 94 oD oO oS AHT Add Halfword Three-Address 95 oD oO oS SHT Subtract Halfword Three-Address 96 oD oO oS MHT Multiply Halfword Three-Address 97 oD oO oS DHT Divide Halfword Three-Address 9B oD oO oS XHT XOR Halfword Three-Address 9C oD oO oS NHT AND Halfword Three-Address 9D oD oO oS OHT OR Halfword Three-Address 9E oD oO oS MEHT Multiply Extensibly Halfword Three-Address 9F oD oO oS DEHT Divide Extensibly Halfword Three-Address A4 oD oO oS AT Add Three-Address A5 oD oO oS ST Subtract Three-Address A6 oD oO oS MT Multiply Three-Address A7 oD oO oS DT Divide Three-Address AB oD oO oS XT XOR Three-Address AC oD oO oS NT AND Three-Address AD oD oO oS OT OR Three-Address AE oD oO oS MET Multiply Extensibly Three-Address AF oD oO oS DET Divide Extensibly Three-Address B4 oD oO oS ALT Add Long Three-Address B5 oD oO oS SLT Subtract Long Three-Address B6 oD oO oS MLT Multiply Long Three-Address B7 oD oO oS DLT Divide Long Three-Address BB oD oO oS XLT XOR Long Three-Address BC oD oO oS NLT AND Long Three-Address BD oD oO oS OLT OR Long Three-Address BE oD oO oS MELT Multiply Extensibly Long Three-Address BF oD oO oS DELT Divide Extensibly Long Three-Address C4 oD oO oS AMT Add Medium Three-Address C5 oD oO oS SMT Subtract Medium Three-Address C6 oD oO oS MMT Multiply Medium Three-Address C7 oD oO oS DMT Divide Medium Three-Address CC oD oO oS AFT Add Floating Three-Address CD oD oO oS SFT Subtract Floating Three-Address CE oD oO oS MFT Multiply Floating Three-Address CF oD oO oS DFT Divide Floating Three-Address D4 oD oO oS ADT Add Double Three-Address D5 oD oO oS SDT Subtract Double Three-Address D6 oD oO oS MDT Multiply Double Three-Address D7 oD oO oS DDT Divide Double Three-Address DC oD oO oS AQT Add Quad Three-Address DD oD oO oS SQT Subtract Quad Three-Address DE oD oO oS MQT Multiply Quad Three-Address DF oD oO oS DQT Divide Quad Three-Address E000 pL oD oO oS MESTPT Multiply Extensibly and Store Packed Three-Address E004 pL oD oO oS APT Add Packed Three-Address E005 pL oD oO oS SPT Subtract Packed Three-Address E006 pL oD oO oS MPT Multiply Packed Three-Address E007 pL oD oO oS DPT Divide Packed Three-Address E0A1 oD oS ABSB Absolute Value Byte Two-Address E0A2 oD oS INVB Invert Byte Two-Address E0A3 oD oS NEGB Negate Byte Two-Address E0A4 oD oO oS NB Normalize Byte Three-Address E0A9 oD oS ABSH Absolute Value Halfword Two-Address E0AA oD oS INVH Invert Halfword Two-Address E0AB oD oS NEGH Negate Halfword Two-Address E0AC oD oO oS NH Normalize Halfword Three-Address E0B1 oD oS ABS Absolute Value Two-Address E0B2 oD oS INV Invert Two-Address E0B3 oD oS NEG Negate Two-Address E0B4 oD oO oS N Normalize Three-Address E0B9 oD oS ABSL Absolute Value Long Two-Address E0BA oD oS INVL Invert Long Two-Address E0BB oD oS NEGL Negate Long Two-Address E0BC oD oO oS NL Normalize Long Three-Address E0C0 sL oD oS SHLBT Shift Left Byte Two-Address E0C1 sL oD oS SHRBT Shift Right Byte Two-Address E0C3 sL oD oS ASRBT Arithmetic Shift Right Byte Two-Address E0C4 sL oD oS ROLBT Rotate Left Byte Two-Address E0C5 sL oD oS RORBT Rotate Right Byte Two-Address E0C6 sL oD oS RLCBT Rotate Left through Carry Byte Two-Address E0C7 sL oD oS RRCBT Rotate Right through Carry Byte Two-Address E0C8 sL oD oS SHLHT Shift Left Halfword Two-Address E0C9 sL oD oS SHRHT Shift Right Halfword Two-Address E0CB sL oD oS ASRHT Arithmetic Shift Right Halfword Two-Address E0CC sL oD oS ROLHT Rotate Left Halfword Two-Address E0CD sL oD oS RORHT Rotate Right Halfword Two-Address E0CE sL oD oS RLCHT Rotate Left through Carry Halfword Two-Address E0CF sL oD oS RRCHT Rotate Right through Carry Halfword Two-Address E0D0 sL oD oS SHLT Shift Left Two-Address E0D1 sL oD oS SHRT Shift Right Two-Address E0D3 sL oD oS ASRT Arithmetic Shift Right Two-Address E0D4 sL oD oS ROLT Rotate Left Two-Address E0D5 sL oD oS RORT Rotate Right Two-Address E0D6 sL oD oS RLCT Rotate Left through Carry Two-Address E0D7 sL oD oS RRCT Rotate Right through Carry Two-Address E0D8 sL oD oS SHLLT Shift Left Long Two-Address E0D9 sL oD oS SHRLT Shift Right Long Two-Address E0DB sL oD oS ASRLT Arithmetic Shift Right Long Two-Address E0DC sL oD oS ROLLT Rotate Left Long Two-Address E0DD sL oD oS RORLT Rotate Right Long Two-Address E0DE sL oD oS RLCLT Rotate Left through Carry Long Two-Address E0DF sL oD oS RRCLT Rotate Right through Carry Long Two-Address E104 vL oD oO oS VAB Vector Add Byte E105 vL oD oO oS VSB Vector Subtract Byte E10B vL oD oO oS VXB Vector XOR Byte E10C vL oD oO oS VNB Vector AND Byte E10D vL oD oO oS VOB Vector OR Byte E114 vL oD oO oS VAH Vector Add Halfword E115 vL oD oO oS VSH Vector Subtract Halfword E116 vL oD oO oS VMH Vector Multiply Halfword E117 vL oD oO oS VDH Vector Divide Halfword E11B vL oD oO oS VXH Vector XOR Halfword E11C vL oD oO oS VNH Vector AND Halfword E11D vL oD oO oS VOH Vector OR Halfword E11E vL oD oO oS VMEH Vector Multiply Extensibly Halfword E11F vL oD oO oS VDEH Vector Divide Extensibly Halfword E124 vL oD oO oS VA Vector Add E125 vL oD oO oS VS Vector Subtract E126 vL oD oO oS VM Vector Multiply E127 vL oD oO oS VD Vector Divide E12B vL oD oO oS VX Vector XOR E12C vL oD oO oS VN Vector AND E12D vL oD oO oS VO Vector OR E12E vL oD oO oS VME Vector Multiply Extensibly E12F vL oD oO oS VDE Vector Divide Extensibly E134 vL oD oO oS VAL Vector Add Long E135 vL oD oO oS VSL Vector Subtract Long E136 vL oD oO oS VML Vector Multiply Long E137 vL oD oO oS VDL Vector Divide Long E13B vL oD oO oS VXL Vector XOR Long E13C vL oD oO oS VNL Vector AND Long E13D vL oD oO oS VOL Vector OR Long E13E vL oD oO oS VMEL Vector Multiply Extensibly Long E13F vL oD oO oS VDEL Vector Divide Extensibly Long E144 vL oD oO oS VAM Vector Add Medium E145 vL oD oO oS VSM Vector Subtract Medium E146 vL oD oO oS VMM Vector Multiply Medium E147 vL oD oO oS VDM Vector Divide Medium E14C vL oD oO oS VAF Vector Add Floating E14D vL oD oO oS VSF Vector Subtract Floating E14E vL oD oO oS VMF Vector Multiply Floating E14F vL oD oO oS VDF Vector Divide Floating E154 vL oD oO oS VAD Vector Add Double E155 vL oD oO oS VSD Vector Subtract Double E156 vL oD oO oS VMD Vector Multiply Double E157 vL oD oO oS VDD Vector Divide Double E15C vL oD oO oS VAQ Vector Add Quad E15D vL oD oO oS VSQ Vector Subtract Quad E15E vL oD oO oS VMQ Vector Multiply Quad E15F vL oD oO oS VDQ Vector Divide Quad E400 oD oS SINMT Sine Medium Two-Address E401 oD oS COSMT Cosine Medium Two-Address E402 oD oS TANMT Tangent Medium Two-Address E404 oD oS ASNMT Arcsine Medium Two-Address E405 oD oS ACSMT Arccosine Medium Two-Address E406 oD oS ATNMT Arctangent Medium Two-Address E408 oD oS SINHMT Hyperbolic Sine Medium Two-Address E409 oD oS COSHMT Hyperbolic Cosine Medium Two-Address E40A oD oS TANHMT Hyperbolic Tangent Medium Two-Address E40C oD oS ASNHMT Inverse Hyperbolic Sine Medium Two-Address E40D oD oS ACSHMT Inverse Hyperbolic Cosine Medium Two-Address E40E oD oS ATNHMT Inverse Hyperbolic Tangent Medium Two-Address E410 oD oS SQRMT Square Root Medium Two-Address E411 oD oS QBRMT Cube Root Medium Two-Address E412 oD oS LOGMT Logarithm Medium Two-Address E413 oD oS EXPMT Exponential Medium Two-Address E415 oD oS ABSMT Absolute Value Medium Two-Address E416 oD oS SGNMT Signum Medium Two-Address E417 oD oS NEGMT Negate Medium Two-Address E420 oD oS SINFT Sine Floating Two-Address E421 oD oS COSFT Cosine Floating Two-Address E422 oD oS TANFT Tangent Floating Two-Address E424 oD oS ASNFT Arcsine Floating Two-Address E425 oD oS ACSFT Arccosine Floating Two-Address E426 oD oS ATNFT Arctangent Floating Two-Address E428 oD oS SINHFT Hyperbolic Sine Floating Two-Address E429 oD oS COSHFT Hyperbolic Cosine Floating Two-Address E42A oD oS TANHFT Hyperbolic Tangent Floating Two-Address E42C oD oS ASNHFT Inverse Hyperbolic Sine Floating Two-Address E42D oD oS ACSHFT Inverse Hyperbolic Cosine Floating Two-Address E42E oD oS ATNHFT Inverse Hyperbolic Tangent Floating Two-Address E430 oD oS SQRFT Square Root Floating Two-Address E431 oD oS QBRFT Cube Root Floating Two-Address E432 oD oS LOGFT Logarithm Floating Two-Address E433 oD oS EXPFT Exponential Floating Two-Address E435 oD oS ABSFT Absolute Value Floating Two-Address E436 oD oS SGNFT Signum Floating Two-Address E437 oD oS NEGFT Negate Floating Two-Address E440 oD oS SINDT Sine Double Two-Address E441 oD oS COSDT Cosine Double Two-Address E442 oD oS TANDT Tangent Double Two-Address E444 oD oS ASNDT Arcsine Double Two-Address E445 oD oS ACSDT Arccosine Double Two-Address E446 oD oS ATNDT Arctangent Double Two-Address E448 oD oS SINHDT Hyperbolic Sine Double Two-Address E449 oD oS COSHDT Hyperbolic Cosine Double Two-Address E44A oD oS TANHDT Hyperbolic Tangent Double Two-Address E44C oD oS ASNHDT Inverse Hyperbolic Sine Double Two-Address E44DT oD oS ACSHDT Inverse Hyperbolic Cosine Double Two-Address E44E oD oS ATNHDT Inverse Hyperbolic Tangent Double Two-Address E450 oD oS SQRDT Square Root Double Two-Address E451 oD oS QBRDT Cube Root Double Two-Address E452 oD oS LOGDT Logarithm Double Two-Address E453 oD oS EXPDT Exponential Double Two-Address E455 oD oS ABSDT Absolute Value Double Two-Address E456 oD oS SGNDT Signum Double Two-Address E457 oD oS NEGDT Negate Double Two-Address E460 oD oS SINQ Sine Quad Two-Address E461 oD oS COSQ Cosine Quad Two-Address E462 oD oS TANQ Tangent Quad Two-Address E4E4 oD oS ASNQ Arcsine Quad Two-Address E465 oD oS ACSQ Arccosine Quad Two-Address E466 oD oS ATNQ Arctangent Quad Two-Address E468 oD oS SINHQ Hyperbolic Sine Quad Two-Address E469 oD oS COSHQ Hyperbolic Cosine Quad Two-Address E46A oD oS TANHQ Hyperbolic Tangent Quad Two-Address E46C oD oS ASNHQ Inverse Hyperbolic Sine Quad Two-Address E46DT oD oS ACSHQT Inverse Hyperbolic Cosine Quad Two-Address E46E oD oS ATNHQT Inverse Hyperbolic Tangent Quad Two-Address E470 oD oS SQRQT Square Root Quad Two-Address E471 oD oS QBRQT Cube Root Quad Two-Address E472 oD oS LOGQT Logarithm Quad Two-Address E473 oD oS EXPQT Exponential Quad Two-Address E475 oD oS ABSQT Absolute Value Quad Two-Address E476 oD oS SGNQT Signum Quad Two-Address E477 oD oS NEGQT Negate Quad Two-Address 6484 oD oO oS AMBT Add Byte to Medium Three-Address 6485 oD oO oS SMBT Subtract Byte from Medium Three-Address 6486 oD oO oS MMBT Multiply Medium by Byte Three-Address 6487 oD oO oS DMBT Divide Medium by Byte Three-Address 648C oD oO oS AMHT Add Halfword to Medium Three-Address 648D oD oO oS SMHT Subtract Halfword from Medium Three-Address 648E oD oO oS MMHT Multiply Medium by Halfword Three-Address 648F oD oO oS DMHT Divide Medium by Halfword Three-Address 6494 oD oO oS AMIT Add Integer to Medium Three-Address 6495 oD oO oS SMIT Subtract Integer from Medium Three-Address 6496 oD oO oS MMIT Multiply Medium by Integer Three-Address 6497 oD oO oS DMIT Divide Medium by Integer Three-Address 649C oD oO oS AMLT Add Long to Medium Three-Address 649D oD oO oS SMLT Subtract Long from Medium Three-Address 649E oD oO oS MMLT Multiply Medium by Long Three-Address 649F oD oO oS DMLT Divide Medium by Long Three-Address 64A4 oD oO oS AFBT Add Byte to Floating Three-Address 64A5 oD oO oS SFBT Subtract Byte from Floating Three-Address 64A6 oD oO oS MFBT Multiply Floating by Byte Three-Address 64A7 oD oO oS DFBT Divide Floating by Byte Three-Address 64AC oD oO oS AFHT Add Halfword to Floating Three-Address 64AD oD oO oS SFHT Subtract Halfword from Floating Three-Address 64AE oD oO oS MFHT Multiply Floating by Halfword Three-Address 64AF oD oO oS DFHT Divide Floating by Halfword Three-Address 64B4 oD oO oS AFIT Add Integer to Floating Three-Address 64B5 oD oO oS SFIT Subtract Integer from Floating Three-Address 64B6 oD oO oS MFIT Multiply Floating by Integer Three-Address 64B7 oD oO oS DFIT Divide Floating by Integer Three-Address 64BC oD oO oS AFLT Add Long to Floating Three-Address 64BD oD oO oS SFLT Subtract Long from Floating Three-Address 64BE oD oO oS MFLT Multiply Floating by Long Three-Address 64BF oD oO oS DFLT Divide Floating by Long Three-Address 64C4 oD oO oS ADBT Add Byte to Double Three-Address 64C5 oD oO oS SDBT Subtract Byte from Double Three-Address 64C6 oD oO oS MDBT Multiply Double by Byte Three-Address 64C7 oD oO oS DDBT Divide Double by Byte Three-Address 64CC oD oO oS ADHT Add Halfword to Double Three-Address 64CD oD oO oS SDHT Subtract Halfword from Double Three-Address 64CE oD oO oS MDHT Multiply Double by Halfword Three-Address 64CF oD oO oS DDHT Divide Double by Halfword Three-Address 64D4 oD oO oS ADIT Add Integer to Double Three-Address 64D5 oD oO oS SDIT Subtract Integer from Double Three-Address 64D6 oD oO oS MDIT Multiply Double by Integer Three-Address 64D7 oD oO oS DDIT Divide Double by Integer Three-Address 64DC oD oO oS ADLT Add Long to Double Three-Address 64DD oD oO oS SDLT Subtract Long from Double Three-Address 64DE oD oO oS MDLT Multiply Double by Long Three-Address 64DF oD oO oS DDLT Divide Double by Long Three-Address 64E4 oD oO oS AQBT Add Byte to Quad Three-Address 64E5 oD oO oS SQBT Subtract Byte from Quad Three-Address 64E6 oD oO oS MQBT Multiply Quad by Byte Three-Address 64E7 oD oO oS DQBT Divide Quad by Byte Three-Address 64EC oD oO oS AQHT Add Halfword to Quad Three-Address 64ED oD oO oS SQHT Subtract Halfword from Quad Three-Address 64EE oD oO oS MQHT Multiply Quad by Halfword Three-Address 64EF oD oO oS DQHT Divide Quad by Halfword Three-Address 64F4 oD oO oS AQIT Add Integer to Quad Three-Address 64F5 oD oO oS SQIT Subtract Integer from Quad Three-Address 64F6 oD oO oS MQIT Multiply Quad by Integer Three-Address 64F7 oD oO oS DQIT Divide Quad by Integer Three-Address 64FC oD oO oS AQLT Add Long to Quad Three-Address 64FD oD oO oS SQLT Subtract Long from Quad Three-Address 64FE oD oO oS MQLT Multiply Quad by Long Three-Address 64FF oD oO oS DQLT Divide Quad by Long Three-Address E604 oM oD oO oS ABSVT Add Byte Short Vector Three-Address E605 oM oD oO oS SBSVT Subtract Byte Short Vector Three-Address E60D oM oD oO oS XBSVT XOR Byte Short Vector Three-Address E60E oM oD oO oS NBSVT AND Byte Short Vector Three-Address E60F oM oD oO oS OBSVT OR Byte Short Vector Three-Address E614 oM oD oO oS AHSVT Add Halfword Short Vector Three-Address E615 oM oD oO oS SHSVT Subtract Halfword Short Vector Three-Address E616 oM oD oO oS MHSVT Multiply Halfword Short Vector Three-Address E617 oM oD oO oS DHSVT Divide Halfword Short Vector Three-Address E61D oM oD oO oS XHSVT XOR Halfword Short Vector Three-Address E61E oM oD oO oS NHSVT AND Halfword Short Vector Three-Address E61F oM oD oO oS OHSVT OR Halfword Short Vector Three-Address E624 oM oD oO oS ASVT Add Short Vector Three-Address E625 oM oD oO oS SSVT Subtract Short Vector Three-Address E626 oM oD oO oS MSVT Multiply Short Vector Three-Address E627 oM oD oO oS DSVT Divide Short Vector Three-Address E62D oM oD oO oS XSVT XOR Short Vector Three-Address E62E oM oD oO oS NSVT AND Short Vector Three-Address E62F oM oD oO oS OSVT OR Short Vector Three-Address E634 oM oD oO oS ALSVT Add Long Short Vector Three-Address E635 oM oD oO oS SLSVT Subtract Long Short Vector Three-Address E636 oM oD oO oS MLSVT Multiply Long Short Vector Three-Address E637 oM oD oO oS DLSVT Divide Long Short Vector Three-Address E63D oM oD oO oS XLSVT XOR Long Short Vector Three-Address E63E oM oD oO oS NLSVT AND Long Short Vector Three-Address E63F oM oD oO oS OLSVT OR Long Short Vector Three-Address E644 oM oD oO oS ASMSVT Add Small Short Vector Three-Address E645 oM oD oO oS SSMSVT Subtract Small Short Vector Three-Address E646 oM oD oO oS MSMSVT Multiply Small Short Vector Three-Address E647 oM oD oO oS DSMSVT Divide Small Short Vector Three-Address E654 oM oD oO oS AFSVT Add Floating Short Vector Three-Address E655 oM oD oO oS SFSVT Subtract Floating Short Vector Three-Address E656 oM oD oO oS MFSVT Multiply Floating Short Vector Three-Address E657 oM oD oO oS DFSVT Divide Floating Short Vector Three-Address E664 oM oD oO oS ADSVT Add Double Short Vector Three-Address E665 oM oD oO oS SDSVT Subtract Double Short Vector Three-Address E666 oM oD oO oS MDSVT Multiply Double Short Vector Three-Address E667 oM oD oO oS DDSVT Divide Double Short Vector Three-Address E674 oM oD oO oS AQSVT Add Quad Short Vector Three-Address E675 oM oD oO oS SQSVT Subtract Quad Short Vector Three-Address E676 oM oD oO oS MQSVT Multiply Quad Short Vector Three-Address E677 oM oD oO oS DQSVT Divide Quad Short Vector Three-Address
In the column after the opcode, the optional fields used by the instruction are indicated. Thus, oD oS means that the instruction will have two operands, the first the destination operand, the second the source operand. oO stands for the extra operand in a three-address instruction; oT for a translate table, and oE for an integer containing the decimal exponent value for the instructions that convert between an integer power-of-ten exponent and a packed decimal mantissa on the one hand and a floating-point number on the other. sL indicates a one-byte string length field, vL indicates the two-byte vector length field, pL indicates a one-byte field indicating the length of each of two packed decimal operands, and pT indicates the two-byte field using five bits each to indicate the lengths of each of three packed decimal operands.
In the convert instructions, sL corresponds to the size field, and vL to the length field.
In the three-address normalize instructions, the normalized version of the source argument is stored in the operand argument, and the number of shifts is stored in the destination argument. For all the normalize instructions, regardless of the type of the instruction, the number of shifts, which is the destination argument, is a 32-bit word integer when stored in memory.
In the vector instructions, a register argument instead of a memory argument can be used for the source or operand operands; when this is done, the contents of the one register specified is used as a constant value applied to the calculation for the entire vector.
For the instructions for loading or storing from a base register, the destination argument must be a register argument, and can have only the values from 0 to 31. For the short vector instructions, where a register argument is specified, it must have a value from 0 to 15, as it would refer to one of the sixteen short vector registers.
For packed decimal instructions, in the three-address case, the convention in other address modes is followed that each length field contains one less than the length of the operand in digits. In the two-address case, the four-bit length fields instead contain one less than the length of the operand in bytes. In the SEBI instruction, the sL field contains the three bits that indicate the operation to perform, followed by the five bits that indicate the round to perform it in. In general, note that string lengths and shift counts are treated as suffixes of the opcode, not as orthogonal operands; this is partly a consequence of the fact that immediate operands have a one-byte prefix followed by a full-length immediate operand, instead of being a single byte with six bits of data as on the Digital Equipment Corporation's VAX series of computers.
To avoid the list of instructions taking up too much space, the less important instructions available in this mode are simply shown in the compact tablular form below:
620 621 622 623 624 625 626
SFSW SWMDE MESTCD CVCDB 0
SFC RPC CMDE CCD CVCDH RCDC 1
SFMV RPME MVMDE MVCD CVCDW RCDME 2
RPDE DSTRCD CVCDL RCDDE 3
SFA RPA AMDE ACD CVCDM RCDA 4
SFS RPS SMDE SCD CVCDF RCDS 5
SFM RPM MMDE MCD CVCDD RCDM 6
SFD RPD DMDE DCD CVCDQ RCDD 7
SFSWH SFSWL SWDDE CVBCD 8
SFCH SFCL RPCL CDDE CVHCD RCDCL 9
SFMVH SFMVL RPMEL MVDDE PCD CVWCD RCDMEL A
RPDEL UCD CVLCD RCDDEL B
SFAH SFAL RPAL ADDE CVMCD RCDAL C
SFSH SFSL RPSL SDDE CVFCD RCDSL D
SFMH SFML RPML MDDE PHCD CVDCD RCDML E
SFDH SFDL RPDL DDDE UHCD CVQCD RCDDL F
E20 E21 E22 E23 E24 E26
MESTCDT 0
1
RPMET RCDMET 2
RPDET DSTRCDT RCDDET 3
SFAT RPAT AMDET ACDT RCDAT 4
SFST RPST SMDET SCDT RCDST 5
SFMT RPMT MMDET MCDT RCDMT 6
SFDT RPDT DMDET DCDT RCDDT 7
8
9
RPMELT RCDMELT A
RPDELT RCDDELT B
SFAHT SFALT RPALT ADDET RCDALT C
SFSHT SFSLT RPSLT SDDET RCDSLT D
SFMHT SFMLT RPMLT MDDET RCDMLT E
SFDHT DFDLT RPDLT DDDET RCDDLT F
628 629 62A 62B 62C
SFMEU MEUM MEUL 0
SFDEU DEUM DEUL 1
SFMVU MVUM MVUL MVMDE 2
3
SFAU AUM AUL AUMDE 4
SFSU SUM SUL SUMDE 5
SFMU MUM MUL MUMDE 6
SFDU DUM DUL DUMDE 7
SFMEUH SFMEUL MEU MEUQ 8
SFDEUH SFDEUL DEU DEUQ 9
SFMVUH SFMVUL MVU MVUQ MVDDE A
B
SFAUH SFAUL AU AUQ AUDDE C
SFSUH SFSUL SU SUQ SUDDE D
SFMUH SFMUL MU MUQ MUDDE E
SFDUH SFDUL DU DUQ DUDDE F
E28 E29 E2A E2B E2C
SFMEUT MEUMT MEULT 0
SFDEUT DEUMT DEULT 1
2
3
SFAUT AUMT AULT AUMDET 4
SFSUT SUMT SULT SUMDET 5
SFMUT MUMT MULT MUMDET 6
SFDUT DUMT DULT DUMDET 7
SFMEUHT SFMEULT MEUT MEUQT 8
SFDEUHT SFDEULT DEUT DEUQT 9
A
B
SFAUHT SFAULT AUT AUQT AUDDET C
SFSUHT SFSULT SUT SUQT SUDDET D
SFMUHT SFMULT MUT MUQT MUDDET E
SFDUHT SFDULT DUT DUQT DUDDET F
These include the instructions for the use of the simple floating type, register packed decimal, decimal exponent floating-point, and compressed decimal, as well as unnormalized floating-point operation.
In addition, vectorial versions of the single-operand floating-point functions have opcodes of the form E5xx and vectorial versions of the short vector operations have opcodes of the form E7xx, except in the case of such operations as move, swap, or set mask bit, which do not change to three-address form when vectorized; these will have the form 67xx. The shuffle operation does not vectorize. These may involve the initiation of one operation per cycle in a pipelined fashion at best, since even in the highest-end implementations of this architecture envisaged, only one copy of the applicable ALUs is present. The same implies to vectorized packed decimal instructions: E3xx is used for the vectorized versions of the instructions shown above, except where no operand argument can be added, in which case 63xx is used.