Classic RISC architectures perform all their operations between operands in registers, with only load and store instructions accessing memory. For an indexed load or store, a separate address calculation instruction is required.
If one modifies the basic RISC instruction so that the instructions do even less, by having the operate instruction always work with operands in accumulators, so that separate load and store instructions are required even to access a register, one can actually obtain an architecture that is nearly equivalent to the most complex form of CISC architecture, the three-address machine.
In this case, however, one tenet of the original RISC architecture needs to be abandoned; since operate instructions do so little, they need to be shorter than memory-reference instructions.
The following diagram illustrates the principal instruction formats for this mode:
The first line illustrates the address calculation instruction. In this instruction, the P bit determines whether the three-bit sB field refers to the corresponding base register or to the corresponding scratchpad register. In either case, the contents of the register indicated are concatenated with the 15-bit address in the instruction to form a 47-bit physical address. This effective address then has the contents of the B accumulator added to it, and the resulting indexed pointer is stored in the pointer register indicated by the three-bit dP field.
This instruction leaves the A register cleared after it finishes executing, and may only be executed if the current type is an integer type.
The second line illustrates the instructions for transferring data between the eight registers and the two accumulators:
01000nnn LDAR Load A Register 01001nnn LDBR Load B Register 01010nnn STAR Store A Register 01011nnn STBR Store B Register
The third line illustrates the instructions for transferring data between a memory location indicated by one of the pointer registers, which are a set of eight 64-bit registers containing 47-bit physical addresses padded on the left with zeroes, and which are formed from the full 64-bit width of the pointer scratchpad registers, and the two accumulators:
01100nnn LDAP Load A Pointer 01101nnn LDBP Load B Pointer 01110nnn STAP Store A Pointer 01111nnn STBP Store B Pointer
The fourth line illustrates the memory load and store instructions. In these instructions, the P bit determines whether the three-bit sB field refers to the corresponding base register or to the corresponding scratchpad register. In either case, the contents of the register indicated are concatenated with the 15-bit address in the instruction to form a 47-bit physical address.
10000nnn LDA Load A 10001nnn LDB Load B 10010nnn STA Store A 10011nnn STB Store B
The fifth line illustrates the operate instructions, which have different interpretations depending on whether the current type is a fixed or floating type:
10100000 SWA Swap 10100000 FSW Floating Swap 10100100 ADD Add 10100100 FAD Floating Add 10100101 SUB Subtract 10100101 FSU Floating Subtract 10100110 MUL Multiply 10100110 FML Floating Multiply 10100111 DIV Divide 10100111 FDV Floating Divide 10101011 XOR Exclusive OR 10101100 AND And 10101100 UAD Add Unnormalized 10101101 ORA Or Accumulators 10101101 USU Subtract Unnormalized 10101110 MLX Multiply Extensibly 10101110 UML Multiply Unnormalized 10101111 DVX Divide Extensibly 10101111 UDV Divide Unnormalized
These instructions all calculate A op B, and leave the result in A, with the exception of the swap instructions SWA and FSW, which swap the two accumulators (useful after an operation where operations are to be chained without all results going to a register), the MLX instruction, which multiplies, and produces a double-width product, the most significant part of which goes in the A accumulator, and the DVX instruction, which puts the remainder in A and the quotient in B.
The seventh line illustrates instructions that store the A or B register contents in one of the base registers; the value stored undergoes memory mapping to convert it to a physical pointer before storage, and one greater than the value stored in the base register is stored in the corresponding scratchpad register.
The fifth line illustrates the conditional execution prefix, which indicates when the following instruction is to be executed.
11010001 XL Execute if Low 11010010 XE Execute if Equal 11010011 XLE Execute if Low or Equal 11010100 XH Execute if High 11010101 XNE Execute if Not Equal 11010110 XHE Execute if High or Equal 11010111 XNV Execute if No Overflow 11011000 XV Execute if Overflow 11011010 XC Execute if Carry 11011011 XNC Execute if No Carry
The eighth line illustrates the unconditional jump instruction.
Also present in this mode, but not illustrated, is the instruction that sets the current type:
11101nnn SETT
SETT 0 causes instructions to act on bytes, SETT 1 on halfwords, SETT 2 on full 32-bit words, and SETT 3 on 64-bit doublewords. SETT 4 causes instructions to have operands of the Medium or Extended type, three or five halfwords aligned on a halfword boundary, depending on the current floating-point format, SETT 5 causes instructions to work on single-precision quantities, SETT 6 double precision, and SETT 7 quadruple precision.
The ninth line illustrates the jump to pointer instruction, allowing indexed jump instructions. Absent a pre-indexed indirect mode, it does still mean that a computed GO TO takes two jumps to implement, as the index is now in to a jump table rather than an address table.
Finally, the instruction 1111nnnn is used for special functions such as input-output or switching to other instruction modes.