This mode of operation uses the sixty-four supplementary registers, both integer and floating-point, for the ordinary register functions of programs. The basic register set usually used by the computer is left untouched.
This facilitates conversion of programs from other computer architectures in which the same set of registers are used for arithmetic and as index registers and as base registers. In addition, the partially disjoint nature of the register complement used in this mode with respect to that used in other modes facilitates using the execution of single instructions in this mode as a technique of emulating other architectures. Of course, register renaming could achieve the same result, but by remaining within a single register set, implementation dependencies and recourse to privileged operations is avoided.
In this mode, memory-reference instructions have the form:
The mode bits for each operand in two-address and three-address scalar memory-reference instructions have the following meaning:
00: Register 01: Memory 11: Immediate
For the two-address and three-address vector memory-reference instructions, the mode bits have this significance:
00: Supplementary Registers 01: Vector Register 10: Vector Scratchpad 11: Memory
and for a memory operand, the six bits of the register field indicate a supplementary register that functions as an index register (or it is zero for no indexing), for a vector scratchpad operand, the six bits indicate which element of the long vector scratchpad is used, for a vector register operand, the last three bits indicate the vector register used, and where the supplementary registers are a vector operand, the register field is not used.
In a memory operand, the I bit indicates indirect addressing, and the P bit, if set when the I bit is also set, and when a nonzero value for the corresponding index register is used, indicates post-indexed indirect addressing.
Otherwise unused combinations of address mode bits allow the extended operate instructions to be present in this mode without using six-bit opcode translation, using opcodes which overlap those of the floating-point instructions, and their formats in this mode are as follows:
The packed decimal and string operate instructions have this form in this mode:
Note that the source operand of the type conversion instructions cannot be indexed; this capability was omitted in order to avoid adding an extra 32 bits to the instruction.
The short vector instructions have the following form in this mode:
Note that if the M bit is not set, so that no mask register is used, the word in which the mask register is specified is omitted from the instruction.
The Define Extended Translate and Extended Translate instructions have this form in general register mode:
Other standard operate instructions, such as the shift and jump instructions, have the following form in this mode:
and, finally, the cache-internal parallel computing setup instructions have this form in this mode:
