In this mode, memory-reference instructions have the form:
In aligned instruction mode, all instructions must be 32 bits in length, although an instruction can contain two register to register operations. This provides for rapid and straightforward instruction decoding, and reduces the overhead of indicating instruction parallelism.
The operate instructions that are available in this mode have the form shown below:
Where an instruction was of a type originally 16 bits in length, the second half of the instruction may contain, as shown in the diagrams, a register to register instruction in its last 13 bits. The first bit of the second 16-bit portion of the instruction indicates that the first half of the instruction may be executed in parallel with the preceding instructions, and in the case when a register to register instruction is in the second half of the instruction, the third bit of the second 16-bit portion indicates that the second half of the instruction may be executed in parallel with the preceding instructions. In both cases, parallelism extends backwards until the most recent instruction which indicated it could not be executed in parallel with the instructions that preceded it.
The opcodes 0000111 and 0111000 in the op2 field can be used as no-operation codes for the second half of the instruction.
Also, if the second half of the instruction begins with P1P1 instead of P0P, the last 12 bits of the instruction can match those of a floating single-operand instruction, a single-operand instruction, or a normalize instruction, for one of these operations to be performed in the second half of the instruction.
As well, if the second half of the instruction begins with P1P0, then that half of the instruction uses the same scratchpad areas in memory as are used in the stateless scratchpad mode.
The op2 field in this instruction supplies the last three bits of a seven-bit opcode; the first four bits of the opcode used for the operation in the second half of the instruction are derived from the first four bits of the op1 field according to the following table:
0000, 0001 0000 0010, 0011 0010 0100, 0101 0100 0110, 0111 0110 1000 1000 1001 1001 1010 1010 1011 1011
thus, only the basic arithmetic operations are used in the second half of instructions of this type, and this kind of second half can only follow a register to register instruction, not a single-operand instruction.
The following diagram illustrates the form of the various available types of second halves for instructions:
Note that in this mode, the decimal, character, and short vector instructions are all not available.