In this mode, memory-reference instructions have two formats:
three-address and two-address.
The mode of each operand of the instruction can be specified independently, and is interpreted according to the following encoding:
00: Register 01: Memory 10: Indirect (post-indexed) 11: Post-increment indexed
In the case of the register mode, the field containing the base register for a memory access contains instead the register serving as the operand, and the index register field contains zero. Or, the index register field can contain a nonzero value, in which case it indicates an addressing mode:
000: Register 001: Register indirect 010: Register indirect post-increment 011: Register indirect post-decrement 111: Immediate
In immediate mode, the operand value is embedded in the instruction itself. If 64-bit addressing is in effect, register indirect addressing involves a register pair, the first register of which, which must be 0, 2, 4, or 6, is specified in the instruction.
This type of instruction format, of course, owes its inspiration to such machines as the PDP-11 and its successor the VAX, as well as other similar architectures such as the Texas Instruments 9900 microprocessor.
In this mode, the special instructions have the same format as in normal mode.
This mode provides access to the same registers as are used in vector register mode, but with only four formats for memory reference instructions:
The mode of each operand of the instruction can be specified independently, and is interpreted according to the following encoding:
00: Register (or vector register) 01: Scratchpad Register (or vector scratchpad) 10: Memory with Register Index 11: Memory with Scratchpad Index
When a register index is specified, the first three bits of the index register field, not required to specify the index register, are instead used to specify the addressing mode from the following list:
000 Indexed 010 Indirect post-indexed 011 Indirect pre-indexed 100 post-increment indexed 101 post-decrement indexed 110 pre-increment indexed 111 pre-decrement indexed
and, as in other modes, a value of zero for the index register indicates that indexing is not performed.
Since the register modes include the scratchpad register mode, which requires a six-bit field to specify the register, the index register field of the instruction, not the base register field, is used to contain the register where a register is the operand of the instruction.
Note that in this format, memory-to-memory long vector operations are maskable, and also note that the same opcodes as in vector register mode are used for testing the elements of a vector and generating a mask from them.
In this mode, the special instructions have the same format as in vector register mode.
It may also be noted that while this mode does have the advantage over vector register mode that it has fewer basic instruction formats, it does have the disadvantage that even register to register instructions occupy three halfwords of storage. Also, neither multi-way instructions nor the extended operations are available in this mode.
This is another symmetric address mode, although it is oriented towards compact instructions, rather than a generalized instruction format at the cost of an increase in the length of instructions.
The illustration above shows the format of memory-reference instructions in this mode.
Opcodes beginning with 00 are byte instructions; those beginning with 01 may be either halfword or word instructions; those beginning with 100 are floating-point instructions, and those beginning with 101 are double-precision floating-point instructions.
The second-last bit of the type field in the Program Status Block for plain scratchpad modes is used to indicate, if 0, that 01 indicates halfword instructions with 16-bit operands, and if 1, that 01 indicates word instructions with 32-bit operands. The SETT instruction may be used to change this bit.
The first line of the illustration shows the format of the opcode halfword of an instruction. Operations are normally register to register, but two bits indicate the addressing mode for each operand.
00 register operand 01 register field indicates index register; address follows 10 register indirect 11 register indirect with postincrement
The next two lines indicate the forms an address constant may take. If the first bit is zero, a 15-bit displacement field is provided, which is added to the contents of base register zero. If it is 1, then a base register (other than zero) is specified in the address constant, and its constants are added to the 12-bit displacement field. If the base register field is zero, the first 4,096 bytes of the virtual address space are addressed in the absence of indexing.
By using 3 bits like the PDP-11, rather than 4, like the TI 9900, to indicate a register, and 2 bits, like the TI 9900, rather than 4, like the PDP-11, to indicate an addressing mode, the opcode field could be increased to 6 bits in length from 4, providing a minicomputer-like instruction format with a mainframe-like selection of operations. Using base registers to allow a larger address space, however, is an additional complication.