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Aligned Operand Mode

As is apparent from the preceding pages, various alternate operating modes have been devised for this architecture in an attempt to obtain additional opcode space, over and above that available in normal mode, while limiting the required compromises to an acceptable level.

One ingenious idea that allows some opcode space to be obtained from nearly any instruction format without any compromise was used in the SEL 32 series of computers, by Systems Engineering Laboratories. This firm made minicomputers, and it was located in Fort Lauderdale, Florida and NASA was one of its main customers.

Instructions were made more compact by only allowing aligned operands to be addressed. The unused least significant bits of the address in most cases were used to help indicate operand type in the instruction.

This ingenious trick is applied in this architecture for Aligned Operand Mode. The first eight lines of the diagram below show the format of indexed memory reference instructions for the various basic operand types:

Normal memory reference instructions, as usual, are indicated by placing zero in the sX (source index register) field; due to the nature of this diagram, repeating this eight times was avoided. Because the type is partially specified in the second halfword of a memory-reference instruction, it is not possible for the register-to-register instructions to be indicated by setting sB to zero, and so, instead, they have a format that is indicated in a different manner.

Note that this mode will be incompatible with Subdivided Double operation in those cases where it causes double-precision operands to be reduced in size, since address values will not be available for all positions in memory containing an aligned double-precision value.

The remaining two lines show the format of register-to-register instructions in this mode and short shift instructions.

The opcodes of the shift instructions in this mode are:

100xxx   SHLB    Shift Left Byte
101xxx   SHRB    Shift Right Byte

103xxx   ASRB    Arithmetic Shift Right Byte
104xxx   ROLB    Rotate Left Byte
105xxx   RORB    Rotate Right Byte
106xxx   RLCB    Rotate Left through Carry Byte
107xxx   RRCB    Rotate Right through Carry Byte

110xxx   SHLH    Shift Left Halfword
111xxx   SHRH    Shift Right Halfword

113xxx   ASRH    Arithmetic Shift Right Halfword
114xxx   ROLH    Rotate Left Halfword
115xxx   RORH    Rotate Right Halfword
116xxx   RLCH    Rotate Left through Carry Halfword
117xxx   RRCH    Rotate Right through Carry Halfword

120xxx   SHL     Shift Left
121xxx   SHR     Shift Right

123xxx   ASR     Arithmetic Shift Right
124xxx   ROL     Rotate Left
125xxx   ROR     Rotate Right
126xxx   RLC     Rotate Left through Carry
127xxx   RRC     Rotate Right through Carry

070xxx   SHLL    Shift Left Long
071xxx   SHRL    Shift Right Long

133xxx   ASRL    Arithmetic Shift Right Long
134xxx   ROLL    Rotate Left Long
135xxx   RORL    Rotate Right Long
136xxx   RLCL    Rotate Left through Carry Long
137xxx   RRCL    Rotate Right through Carry Long

The operate instructions have the same format as in normal mode.

The opcodes for memory-reference and register-to-register instructions are:

000xxx xxxxxx         041x0x  SWB    Swap Byte
002xxx xxxxxx         043x0x  CB     Compare Byte
004xxx xxxxxx         045x0x  LB     Load Byte
006xxx xxxxxx                 STB    Store Byte
010xxx xxxxxx         051x0x  AB     Add Byte
012xxx xxxxxx         053x0x  SB     Subtract Byte

020xxx xxxxxx         061x0x  IB     Insert Byte
022xxx xxxxxx         063x0x  UCB    Unsigned Compare Byte
024xxx xxxxxx         065x0x  ULB    Unsigned Load Byte
026xxx xxxxxx         067x0x  XB     XOR Byte
030xxx xxxxxx         071x0x  NB     AND Byte
032xxx xxxxxx         073x0x  OB     OR Byte

036xxx xxxxxx         077x0x  STGB   Store if Greater Byte

001xxx xxxxx0 (xx0)   041x1x  SWH    Swap Halfword
003xxx xxxxx0 (xx0)   043x1x  CH     Compare Halfword
005xxx xxxxx0 (xx0)   045x1x  LH     Load Halfword
007xxx xxxxx0 (xx0)           STH    Store Halfword
011xxx xxxxx0 (xx0)   051x1x  AH     Add Halfword
013xxx xxxxx0 (xx0)   053x1x  SH     Subtract Halfword
015xxx xxxxx0 (xx0)   055x1x  MH     Multiply Halfword
017xxx xxxxx0 (xx0)   057x1x  DH     Divide Halfword

021xxx xxxxx0 (xx0)   061x1x  IH     Insert Halfword
023xxx xxxxx0 (xx0)   063x1x  UCH    Unsigned Compare Halfword
025xxx xxxxx0 (xx0)   065x1x  ULH    Unsigned Load Halfword
027xxx xxxxx0 (xx0)   067x1x  XH     XOR Halfword
031xxx xxxxx0 (xx0)   071x1x  NH     AND Halfword
033xxx xxxxx0 (xx0)   073x1x  OH     OR Halfword
035xxx xxxxx0 (xx0)   075x1x  MEH    Multiply Extensibly Halfword
037xxx xxxxx0 (xx0)   077x1x  DEH    Divide Extensibly Halfword

001xxx xxxxx1 (x01)   041x2x  SW     Swap
003xxx xxxxx1 (x01)   043x2x  C      Compare
005xxx xxxxx1 (x01)   045x2x  L      Load
007xxx xxxxx1 (x01)           ST     Store
011xxx xxxxx1 (x01)   051x2x  A      Add
013xxx xxxxx1 (x01)   053x2x  S      Subtract
015xxx xxxxx1 (x01)   055x2x  M      Multiply
017xxx xxxxx1 (x01)   057x2x  D      Divide

023xxx xxxxx1 (x01)   063x2x  UC     Unsigned Compare

027xxx xxxxx1 (x01)   067x2x  X      XOR
031xxx xxxxx1 (x01)   071x2x  N      AND
033xxx xxxxx1 (x01)   073x2x  O      OR
035xxx xxxxx1 (x01)   075x2x  ME     Multiply Extensibly
037xxx xxxxx1 (x01)   077x2x  DE     Divide Extensibly

001xxx xxxxx3 (x11)   041x3x  SWL    Swap Long
003xxx xxxxx3 (x11)   043x3x  CL     Compare Long
005xxx xxxxx3 (x11)   045x3x  LL     Load Long
007xxx xxxxx3 (x11)           STL    Store Long
011xxx xxxxx3 (x11)   051x3x  AL     Add Long
013xxx xxxxx3 (x11)   053x3x  SL     Subtract Long
015xxx xxxxx3 (x11)   055x3x  ML     Multiply Long
017xxx xxxxx3 (x11)   057x3x  DL     Divide Long

023xxx xxxxx3 (x11)   063x3x  UCL    Unsigned Compare Long

027xxx xxxxx3 (x11)   067x3x  XL     XOR Long
031xxx xxxxx3 (x11)   071x3x  NL     AND Long
033xxx xxxxx3 (x11)   073x3x  OL     OR Long
035xxx xxxxx3 (x11)   075x3x  MEL    Multiply Extensibly Long
037xxx xxxxx3 (x11)   077x3x  DEL    Divide Extensibly Long

040xxx xxxxx0 (xx0)   041x4x  SWM    Swap Medium
042xxx xxxxx0 (xx0)   043x4x  CM     Compare Medium
044xxx xxxxx0 (xx0)   045x4x  LM     Load Medium
046xxx xxxxx0 (xx0)           STM    Store Medium
050xxx xxxxx0 (xx0)   051x4x  AM     Add Medium
052xxx xxxxx0 (xx0)   053x4x  SM     Subtract Medium
054xxx xxxxx0 (xx0)   055x4x  MM     Multiply Medium
056xxx xxxxx0 (xx0)   057x4x  DM     Divide Medium

060xxx xxxxx0 (xx0)   061x4x  MEUM   Multiply Extensibly Unnormalized Medium
062xxx xxxxx0 (xx0)   063x4x  DEUM   Divide Extensibly Unnormalized Medium
064xxx xxxxx0 (xx0)   065x4x  LUM    Load Unnormalized Medium
066xxx xxxxx0 (xx0)   067x4x  STUM   Store Unnormalized Medium
070xxx xxxxx0 (xx0)   071x4x  AUM    Add Unnormalized Medium
072xxx xxxxx0 (xx0)   073x4x  SUM    Subtract Unnormalized Medium
074xxx xxxxx0 (xx0)   075x4x  MUM    Multiply Unnormalized Medium
076xxx xxxxx0 (xx0)   077x4x  DUM    Divide Unnormalized Medium

040xxx xxxxx1 (x01)   041x5x  SWF    Swap Floating
042xxx xxxxx1 (x01)   043x5x  CF     Compare Floating
044xxx xxxxx1 (x01)   045x5x  LF     Load Floating
046xxx xxxxx1 (x01)           STF    Store Floating
050xxx xxxxx1 (x01)   051x5x  AF     Add Floating
052xxx xxxxx1 (x01)   053x5x  SF     Subtract Floating
054xxx xxxxx1 (x01)   055x5x  MF     Multiply Floating
056xxx xxxxx1 (x01)   057x5x  DF     Divide Floating

060xxx xxxxx1 (x01)   061x5x  MEU    Multiply Extensibly Unnormalized
062xxx xxxxx1 (x01)   063x5x  DEU    Divide Extensibly Unnormalized
064xxx xxxxx1 (x01)   065x5x  LU     Load Unnormalized
066xxx xxxxx1 (x01)   067x5x  STU    Store Unnormalized
070xxx xxxxx1 (x01)   071x5x  AU     Add Unnormalized
072xxx xxxxx1 (x01)   073x5x  SU     Subtract Unnormalized
074xxx xxxxx1 (x01)   075x5x  MU     Multiply Unnormalized
076xxx xxxxx1 (x01)   077x5x  DU     Divide Unnormalized

040xxx xxxxx3 (011)   041x6x  SWD    Swap Double
042xxx xxxxx3 (011)   043x6x  CD     Compare Double
044xxx xxxxx3 (011)   045x6x  LD     Load Double
046xxx xxxxx3 (011)           STD    Store Double
050xxx xxxxx3 (011)   051x6x  AD     Add Double
052xxx xxxxx3 (011)   053x6x  SD     Subtract Double
054xxx xxxxx3 (011)   055x6x  MD     Multiply Double
056xxx xxxxx3 (011)   057x6x  DD     Divide Double

060xxx xxxxx3 (011)   061x6x  MEUD   Multiply Extensibly Unnormalized Double
062xxx xxxxx3 (011)   063x6x  DEUD   Divide Extensibly Unnormalized Double
064xxx xxxxx3 (011)   065x6x  LUD    Load Unnormalized Double
066xxx xxxxx3 (011)   067x6x  STUD   Store Unnormalized Double
070xxx xxxxx3 (011)   071x6x  AUD    Add Unnormalized Double
072xxx xxxxx3 (011)   073x6x  SUD    Subtract Unnormalized Double
074xxx xxxxx3 (011)   075x6x  MUD    Multiply Unnormalized Double
076xxx xxxxx3 (011)   077x6x  DUD    Divide Unnormalized Double

040xxx xxxxx7 (111)   041x7x  SWQ    Swap Quad
042xxx xxxxx7 (111)   043x7x  CQ     Compare Quad
044xxx xxxxx7 (111)   045x7x  LQ     Load Quad
046xxx xxxxx7 (111)           STQ    Store Quad
050xxx xxxxx7 (111)   051x7x  AQ     Add Quad
052xxx xxxxx7 (111)   053x7x  SQ     Subtract Quad
054xxx xxxxx7 (111)   055x7x  MQ     Multiply Quad
056xxx xxxxx7 (111)   057x7x  DQ     Divide Quad

060xxx xxxxx7 (111)   061x7x  MEUQ   Multiply Extensibly Unnormalized Quad
062xxx xxxxx7 (111)   063x7x  DEUQ   Divide Extensibly Unnormalized Quad
064xxx xxxxx7 (111)   065x7x  LUQ    Load Unnormalized Quad
066xxx xxxxx7 (111)   067x7x  STUQ   Store Unnormalized Quad
070xxx xxxxx7 (111)   071x7x  AUQ    Add Unnormalized Quad
072xxx xxxxx7 (111)   073x7x  SUQ    Subtract Unnormalized Quad
074xxx xxxxx7 (111)   075x7x  MUQ    Multiply Unnormalized Quad
076xxx xxxxx7 (111)   077x7x  DUQ    Divide Unnormalized Quad

Aligned Condensed Mode

In this mode, the scratchpad pointer registers are used instead of the normal base registers for memory reference instructions, because the range of addresses reachable from a given base register's contents in the normal memory-reference instructions has been reduced from 65,536 bytes to 32,768 bytes.

As well, only scratchpad pointer registers 2 through 7 are used as base registers, and the unnormalized floating-point instructions (not applicable, in any case, to IEEE-478 compliant arithmetic) are excluded from the normal memory-reference instruction format. They are still available in register-to-register instructions, as well as in condensed instructions and short memory reference instructions if a floating-point type is in use.

This allows the opcode space to be squeezed even further than in Aligned Operand Mode, while still limiting the compromises that need to be made. This allows room both for a 16-bit short memory-reference instruction and a 16-bit instruction containing two register to register operations, which can allow the size of some programs to be nearly cut in half.

Squeezing in the floating-point instructions required splitting up their three-bit opcodes into three separate bits, one of which is in the second halfword of the instruction. The opcodes for the floating-point instructions in this mode are the following:

101xx0 0xxxx0 (xx0)  SWM    Swap Medium
101xx0 1xxxx0 (xx0)  CM     Compare Medium
101xx1 0xxxx0 (xx0)  LM     Load Medium
101xx1 1xxxx0 (xx0)  STM    Store Medium
121xx0 0xxxx0 (xx0)  AM     Add Medium
121xx0 1xxxx0 (xx0)  SM     Subtract Medium
121xx1 0xxxx0 (xx0)  MM     Multiply Medium
121xx1 1xxxx0 (xx0)  DM     Divide Medium

101xx0 0xxxx1 (x01)  SWF    Swap Floating
101xx0 1xxxx1 (x01)  CF     Compare Floating
101xx1 0xxxx1 (x01)  LF     Load Floating
101xx1 1xxxx1 (x01)  STF    Store Floating
121xx0 0xxxx1 (x01)  AF     Add Floating
121xx0 1xxxx1 (x01)  SF     Subtract Floating
121xx1 0xxxx1 (x01)  MF     Multiply Floating
121xx1 1xxxx1 (x01)  DF     Divide Floating

101xx0 0xxxx3 (011)  SWD    Swap Double
101xx0 1xxxx3 (011)  CD     Compare Double
101xx1 0xxxx3 (011)  LD     Load Double
101xx1 1xxxx3 (011)  STD    Store Double
121xx0 0xxxx3 (011)  AD     Add Double
121xx0 1xxxx3 (011)  SD     Subtract Double
121xx1 0xxxx3 (011)  MD     Multiply Double
121xx1 1xxxx3 (011)  DD     Divide Double

101xx0 0xxxx7 (111)  SWQ    Swap Quad
101xx0 1xxxx7 (111)  CQ     Compare Quad
101xx1 0xxxx7 (111)  LQ     Load Quad
101xx1 1xxxx7 (111)  STQ    Store Quad
121xx0 0xxxx7 (111)  AQ     Add Quad
121xx0 1xxxx7 (111)  SQ     Subtract Quad
121xx1 0xxxx7 (111)  MQ     Multiply Quad
121xx1 1xxxx7 (111)  DQ     Divide Quad

The short memory reference instructions have only a four-bit opcode, and the condensed instructions have two four-bit opcodes, which specifies the operation to be performed; they act on the operand type used by the last instruction to specify an operand type.

Type information is handled as in Plain Mutable Scratchpad Mode. It should also be noted that the type is only set by the short format memory reference instructions, and the register to register instructions, described on this page, and not by the long format instructions including long vector instructions described later, even if they use a conventional operand type instead of a type not representable in the three-bit field in the Program Status Block for the last type used such as Register Packed, Simple Floating, or Decimal Exponent.

The four-bit opcodes have two different names in some cases, depending on whether a fixed-point or floating-point type is in use:

0000  SWSP Swap Scratchpad
0001  CSP  Compare Scratchpad
0010  LSP  Load Scratchpad
0011  STSP Store Scratchpad
0100  ASP  Add Scratchpad
0101  SSP  Subtract Scratchpad
0110  MSP  Multiply Scratchpad
0111  DSP  Divide Scratchpad
1000  ISP  Insert Scratchpad                  MEUSP Multiply Extensibly Unnormalized Scratchpad
1001  UCSP Unsigned Compare Scratchpad        DEUSP Divide Extensibly Unnormalized Scratchpad
1010  ULSP Unsigned Load Scratchpad           LUSP  Load Unnormalized Scratchpad
1011  XSP  XOR Scratchpad                     STUSP Store Unnormalized Scratchpad
1100  NSP  AND Scratchpad                     AUSP  Add Unnormalized Scratchpad
1101  OSP  OR Scratchpad                      SUSP  Subtract Unnormalized Scratchpad
1110  MESP Multiply Extensibly Scratchpad     MUSP  Multiply Unnormalized Scratchpad
1111  DESP Divide Extensibly Scratchpad       DUSP  Divide Unnormalized Scratchpad

the selected type being called the scratchpad type, because type selection is most extensively used with the scratchpad instructions, to be described in a later section. This mode follows the pattern used in the plain scratchpad modes.

Both the condensed instructions and the short memory-reference instructions use the appropriate register 0, either arithmetic/index register zero or floating-point register zero, as their destination register. For the short memory-reference instructions, arithmetic/index register 1 serves as the index register if the indexing bit is a 1.

The address is shifted left as appropriate for the data type (one bit for Medium floating-point numbers, aligned on 16-bit boundaries), and the contents of the scratchpad base register corresponding to the type in use are added to it:

000 Byte
001 Halfword
010 Integer
011 Long
100 Medium
101 Floating
110 Double
111 Quad

Aligned Stack Mode

The same measures taken to make more opcode space available, while still leaving eight destination registers and seven index registers (but reducing the number of base registers from seven to six) available which allowed both condensed format instructions and single-halfword memory-reference instructions, can also be used instead to free up space for stack instructions, as shown below:

However, here, the scratchpad base registers, not the scratchpad pointer registers, are used as base registers for the normal memory-reference instructions.

The instructions beginning with a 0 bit consist of one halfword in which three operations are specified. These operations perform arithmetic on a stack, and are as follows:

00000        NOP    no operation
00001 00nnn  MODE   switch to the stack for values of type nnn:

                    000 byte         100 medium
                    001 halfword     101 floating
                    010 integer      110 double
                    011 long         111 quad

00010        DUP    append an extra copy of the current top item
                    on the stack to the top of the stack
00011        DROP   discard the top item on the stack
00100        ADD    replace the top two items on the stack with
                    one item containing their sum
00101        SUB
00110        MUL
00111        DIV
01000        AND
01001        OR
01010        XOR
01011        SWAP   exchange the top two items on the stack

10nnn        PUSH   append the value in register nnn to the top of
                    the stack
11nnn        POP    remove the top item on the stack, and place it
                    in register nnn

The stacks are in memory, and the scratchpad registers are used as the pointers to the stacks of the eight types.

The opcodes of the memory-reference and register-to-register instructions are split into five and two bits in the same fashion as in vector register mode, the first two bits of the opcode being moved to a later position.

The Hewlett-Packard 3000 series computers had a similar mechanism for placing two stack instructions, each six bits in length, in a single sixteen-bit word.


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