In Advanced Compound Mode, the basic memory-reference instructions have the following form:
Note that no large area of opcode space remains for the operate instructions; instead, they, like other less-used instructions, will have an extra 16-bit prefix.
Six-bit opcodes allow access to the basic data types of 8, 16, and 32-bit fixed point, and 32 and 64-bit floating point. In addition to the standard register-to-register, memory reference, and indexed modes, a scratchpad mode is available, where the destination operand is one of registers 0 through 3, and the source one of the 64 supplementary registers. The shift instruction is available in a short 16-bit form as well.
Also shown is a longer instruction format in which opcodes are 12 bits long to permit access to additional data types. The long vector instructions, to be described later, will have a nine-bit opcode.
In the instructions where the opcode is twelve bits long, the most significant six bits of the opcode are in the first halfword, and the least significant six bits of the opcode are in the second halfword. In these instructions with nine-bit opcodes, however, to keep as many of the least significant bits of the opcode contiguous as possible, the first halfword contains the least significant six bits of the opcode, and the second halfword contains the most significant three bits of the opcode. Thus, the opcodes of the instructions in the two basic instruction formats seen so far are shown in the first two columns; and the format with nine-bit opcodes to be seen on a later page is shown in the third column. The fourth column shows opcodes for mixed operation mode, to be described below. The opcodes are:
0x00xx 120400 000xxx 142x00 00xxxx SWB Swap Byte
0x01xx 120400 001xxx 142x01 00xxxx CB Compare Byte
0x02xx 120400 002xxx 142x02 00xxxx LB Load Byte
0x03xx 120400 003xxx 142x03 00xxxx STB Store Byte
0x04xx 120400 004xxx 142x04 00xxxx AB Add Byte
0x05xx 120400 005xxx 142x05 00xxxx SB Subtract Byte
0x10xx 120400 010xxx 142x10 00xxxx IB Insert Byte
0x11xx 120400 011xxx 142x11 00xxxx UCB Unsigned Compare Byte
0x12xx 120400 012xxx 142x12 00xxxx ULB Unsigned Load Byte
0x13xx 120400 013xxx 142x13 00xxxx XB XOR Byte
0x14xx 120400 014xxx 142x14 00xxxx NB AND Byte
0x15xx 120400 015xxx 142x15 00xxxx OB OR Byte
0x17xx 120400 017xxx 142x17 00xxxx STGB Store if Greater Byte
0x20xx 120400 020xxx 142x20 00xxxx SWB Swap Halfword
0x21xx 120400 021xxx 142x21 00xxxx CB Compare Halfword
0x22xx 120400 022xxx 142x22 00xxxx LB Load Halfword
0x23xx 120400 023xxx 142x23 00xxxx STB Store Halfword
0x24xx 120400 024xxx 142x24 00xxxx AB Add Halfword
0x25xx 120400 025xxx 142x25 00xxxx SB Subtract Halfword
0x26xx 120400 026xxx 142x26 00xxxx MH Multiply Halfword
0x27xx 120400 027xxx 142x27 00xxxx DH Divide Halfword
0x30xx 120400 030xxx 142x30 00xxxx IB Insert Halfword
0x31xx 120400 031xxx 142x31 00xxxx UCB Unsigned Compare Halfword
0x32xx 120400 032xxx 142x32 00xxxx ULB Unsigned Load Halfword
0x33xx 120400 033xxx 142x33 00xxxx XB XOR Halfword
0x34xx 120400 034xxx 142x34 00xxxx NB AND Halfword
0x35xx 120400 035xxx 142x35 00xxxx OB OR Halfword
0x36xx 120400 036xxx 142x36 00xxxx MEH Multiply Extensibly Halfword
0x37xx 120400 037xxx 142x37 00xxxx DEH Divide Extensibly Halfword
0x40xx 120400 040xxx 142x40 00xxxx SW Swap
0x41xx 120400 041xxx 142x41 00xxxx C Compare
0x42xx 120400 042xxx 142x42 00xxxx L Load
0x43xx 120400 043xxx 142x43 00xxxx ST Store
0x44xx 120400 044xxx 142x44 00xxxx A Add
0x45xx 120400 045xxx 142x45 00xxxx S Subtract
0x46xx 120400 046xxx 142x46 00xxxx M Multiply
0x47xx 120400 047xxx 142x47 00xxxx D Divide
0x51xx 120400 051xxx 142x51 00xxxx UC Unsigned Compare
0x53xx 120400 053xxx 142x53 00xxxx X XOR
0x54xx 120400 054xxx 142x54 00xxxx N AND
0x55xx 120400 055xxx 142x55 00xxxx O OR
0x56xx 120400 056xxx 142x56 00xxxx ME Multiply Extensibly
0x57xx 120400 057xxx 142x57 00xxxx DE Divide Extensibly
120400 060xxx 142x60 00xxxx 1x00xx SWL Swap Long
120400 061xxx 142x61 00xxxx 1x01xx CL Compare Long
120400 062xxx 142x62 00xxxx 1x02xx LL Load Long
120400 063xxx 142x63 00xxxx 1x03xx STL Store Long
120400 064xxx 142x64 00xxxx 1x04xx AL Add Long
120400 065xxx 142x65 00xxxx 1x05xx SL Subtract Long
120400 066xxx 142x66 00xxxx 1x06xx ML Multiply Long
120400 067xxx 142x67 00xxxx 1x07xx DL Divide Long
120400 070xxx 142x70 00xxxx 1x10xx UCL Unsigned Compare Long
120400 073xxx 142x73 00xxxx 1x13xx XL XOR Long
120400 074xxx 142x74 00xxxx 1x14xx NL AND Long
120400 075xxx 142x75 00xxxx 1x15xx OL OR Long
120400 076xxx 142x76 00xxxx 1x16xx MEL Multiply Extensibly Long
120400 077xxx 142x77 00xxxx 1x17xx DEL Divide Extensibly Long
120401 000xxx 142x00 01xxxx 1x40xx SWM Swap Medium
120401 001xxx 142x01 01xxxx 1x41xx CM Compare Medium
120401 002xxx 142x02 01xxxx 1x42xx LM Load Medium
120401 003xxx 142x03 01xxxx 1x43xx STM Store Medium
120401 004xxx 142x04 01xxxx 1x44xx AM Add Medium
120401 005xxx 142x05 01xxxx 1x45xx SM Subtract Medium
120401 006xxx 142x06 01xxxx 1x46xx MM Multiply Medium
120401 007xxx 142x07 01xxxx 1x47xx DM Divide Medium
120401 010xxx 142x10 01xxxx 1x50xx MEUM Multiply Extensibly Unnormalized Medium
120401 011xxx 142x11 01xxxx 1x51xx DEUM Divide Extensibly Unnormalized Medium
120401 012xxx 142x12 01xxxx 1x52xx LUM Load Unnormalized Medium
120401 013xxx 142x13 01xxxx 1x53xx STUM Store Unnormalized Medium
120401 014xxx 142x14 01xxxx 1x54xx AUM Add Unnormalized Medium
120401 015xxx 142x15 01xxxx 1x55xx SUM Subtract Unnormalized Medium
120401 016xxx 142x16 01xxxx 1x56xx MUM Multiply Unnormalized Medium
120401 017xxx 142x17 01xxxx 1x57xx DUM Divide Unnormalized Medium
0x60xx 120401 020xxx 142x20 01xxxx SWF Swap Floating
0x61xx 120401 021xxx 142x21 01xxxx CF Compare Floating
0x62xx 120401 022xxx 142x22 01xxxx LF Load Floating
0x63xx 120401 023xxx 142x23 01xxxx STF Store Floating
0x64xx 120401 024xxx 142x24 01xxxx AF Add Floating
0x65xx 120401 025xxx 142x25 01xxxx SF Subtract Floating
0x66xx 120401 026xxx 142x26 01xxxx MF Multiply Floating
0x67xx 120401 027xxx 142x27 01xxxx DF Divide Floating
120401 030xxx 142x30 01xxxx 1x60xx MEU Multiply Extensibly Unnormalized
120401 031xxx 142x31 01xxxx 1x61xx DEU Divide Extensibly Unnormalized
120401 032xxx 142x32 01xxxx 1x62xx LU Load Unnormalized
120401 033xxx 142x33 01xxxx 1x63xx STU Store Unnormalized
120401 034xxx 142x34 01xxxx 1x64xx AU Add Unnormalized
120401 035xxx 142x35 01xxxx 1x65xx SU Subtract Unnormalized
120401 036xxx 142x36 01xxxx 1x66xx MU Multiply Unnormalized
120401 037xxx 142x37 01xxxx 1x67xx DU Divide Unnormalized
0x70xx 120401 040xxx 142x40 01xxxx SWD Swap Double
0x71xx 120401 041xxx 142x41 01xxxx CD Compare Double
0x72xx 120401 042xxx 142x42 01xxxx LD Load Double
0x73xx 120401 043xxx 142x43 01xxxx STD Store Double
0x74xx 120401 044xxx 142x44 01xxxx AD Add Double
0x75xx 120401 045xxx 142x45 01xxxx SD Subtract Double
0x76xx 120401 046xxx 142x46 01xxxx MD Multiply Double
0x77xx 120401 047xxx 142x47 01xxxx DD Divide Double
120401 050xxx 142x50 01xxxx 1x70xx MEUD Multiply Extensibly Unnormalized Double
120401 051xxx 142x51 01xxxx 1x71xx DEUD Divide Extensibly Unnormalized Double
120401 052xxx 142x52 01xxxx 1x72xx LUD Load Unnormalized Double
120401 053xxx 142x53 01xxxx 1x73xx STUD Store Unnormalized Double
120401 054xxx 142x54 01xxxx 1x74xx AUD Add Unnormalized Double
120401 055xxx 142x55 01xxxx 1x75xx SUD Subtract Unnormalized Double
120401 056xxx 142x56 01xxxx 1x76xx MUD Multiply Unnormalized Double
120401 057xxx 142x57 01xxxx 1x77xx DUD Divide Unnormalized Double
120401 060xxx 142x60 01xxxx 1x20xx SWQ Swap Quad
120401 061xxx 142x61 01xxxx 1x21xx CQ Compare Quad
120401 062xxx 142x62 01xxxx 1x22xx LQ Load Quad
120401 063xxx 142x63 01xxxx 1x23xx STQ Store Quad
120401 064xxx 142x64 01xxxx 1x24xx AQ Add Quad
120401 065xxx 142x65 01xxxx 1x25xx SQ Subtract Quad
120401 066xxx 142x66 01xxxx 1x26xx MQ Multiply Quad
120401 067xxx 142x67 01xxxx 1x27xx DQ Divide Quad
120401 070xxx 142x70 01xxxx 1x30xx MEUQ Multiply Extensibly Unnormalized Quad
120401 071xxx 142x71 01xxxx 1x31xx DEUQ Divide Extensibly Unnormalized Quad
120401 072xxx 142x72 01xxxx 1x32xx LUQ Load Unnormalized Quad
120401 073xxx 142x73 01xxxx 1x33xx STUQ Store Unnormalized Quad
120401 074xxx 142x74 01xxxx 1x34xx AUQ Add Unnormalized Quad
120401 075xxx 142x75 01xxxx 1x35xx SUQ Subtract Unnormalized Quad
120401 076xxx 142x76 01xxxx 1x36xx MUQ Multiply Unnormalized Quad
120401 077xxx 142x77 01xxxx 1x37xx DUQ Divide Unnormalized Quad
120402 020xxx 142x20 02xxxx SFSWL Simple Floating Swap Halfword
120402 021xxx 142x21 02xxxx SFCL Simple Floating Compare Halfword
120402 022xxx 142x22 02xxxx SFLL Simple Floating Load Halfword
120402 023xxx 142x23 02xxxx SFSTL Simple Floating Store Halfword
120402 024xxx 142x24 02xxxx SFAL Simple Floating Add Halfword
120402 025xxx 142x25 02xxxx SFSL Simple Floating Subtract Halfword
120402 026xxx 142x26 02xxxx SFML Simple Floating Multiply Halfword
120402 027xxx 142x27 02xxxx SFDL Simple Floating Divide Halfword
120402 030xxx 142x30 02xxxx SFMEUH Simple Floating Multiply Extensibly Unnormalized Halfword
120402 031xxx 142x31 02xxxx SFDEUH Simple Floating Divide Extensibly Unnormalized Halfword
120402 032xxx 142x32 02xxxx SFLUH Simple Floating Load Unnormalized Halfword
120402 033xxx 142x33 02xxxx SFSTUH Simple Floating Store Unnormalized Halfword
120402 034xxx 142x34 02xxxx SFAUH Simple Floating Add Unnormalized Halfword
120402 035xxx 142x35 02xxxx SFSUH Simple Floating Subtract Unnormalized Halfword
120402 036xxx 142x36 02xxxx SFMUH Simple Floating Multiply Unnormalized Halfword
120402 037xxx 142x37 02xxxx SFDUH Simple Floating Divide Unnormalized Halfword
120402 040xxx 142x40 02xxxx SFSW Simple Floating Swap
120402 041xxx 142x41 02xxxx SFC Simple Floating Compare
120402 042xxx 142x42 02xxxx SFL Simple Floating Load
120402 043xxx 142x43 02xxxx SFST Simple Floating Store
120402 044xxx 142x44 02xxxx SFA Simple Floating Add
120402 045xxx 142x45 02xxxx SFS Simple Floating Subtract
120402 046xxx 142x46 02xxxx SFM Simple Floating Multiply
120402 047xxx 142x47 02xxxx SFD Simple Floating Divide
120402 050xxx 142x50 02xxxx SFMEU Simple Floating Multiply Extensibly Unnormalized
120402 051xxx 142x51 02xxxx SFDEU Simple Floating Divide Extensibly Unnormalized
120402 052xxx 142x52 02xxxx SFLU Simple Floating Load Unnormalized
120402 053xxx 142x53 02xxxx SFSTU Simple Floating Store Unnormalized
120402 054xxx 142x54 02xxxx SFAU Simple Floating Add Unnormalized
120402 055xxx 142x55 02xxxx SFSU Simple Floating Subtract Unnormalized
120402 056xxx 142x56 02xxxx SFMU Simple Floating Multiply Unnormalized
120402 057xxx 142x57 02xxxx SFDU Simple Floating Divide Unnormalized
120402 060xxx 142x60 02xxxx SFSWL Simple Floating Swap Long
120402 061xxx 142x61 02xxxx SFCL Simple Floating Compare Long
120402 062xxx 142x62 02xxxx SFLL Simple Floating Load Long
120402 063xxx 142x63 02xxxx SFSTL Simple Floating Store Long
120402 064xxx 142x64 02xxxx SFAL Simple Floating Add Long
120402 065xxx 142x65 02xxxx SFSL Simple Floating Subtract Long
120402 066xxx 142x66 02xxxx SFML Simple Floating Multiply Long
120402 067xxx 142x67 02xxxx SFDL Simple Floating Divide Long
120402 070xxx 142x70 02xxxx SFMEUL Simple Floating Multiply Extensibly Unnormalized Long
120402 071xxx 142x71 02xxxx SFDEUL Simple Floating Divide Extensibly Unnormalized Long
120402 072xxx 142x72 02xxxx SFLUL Simple Floating Load Unnormalized Long
120402 073xxx 142x73 02xxxx SFSTUL Simple Floating Store Unnormalized Long
120402 074xxx 142x74 02xxxx SFAUL Simple Floating Add Unnormalized Long
120402 075xxx 142x75 02xxxx SFSUL Simple Floating Subtract Unnormalized Long
120402 076xxx 142x76 02xxxx SFMUL Simple Floating Multiply Unnormalized Long
120402 077xxx 142x77 02xxxx SFDUL Simple Floating Divide Unnormalized Long
120403 001xxx 142x01 03xxxx RPC Register Packed Compare
120403 002xxx 142x02 03xxxx RPME Register Packed Multiply Extensibly
120403 003xxx 142x03 03xxxx RPDE Register Packed Divide Extensibly
120403 004xxx 142x04 03xxxx RPA Register Packed Add
120403 005xxx 142x05 03xxxx RPS Register Packed Subtract
120403 006xxx 142x06 03xxxx RPM Register Packed Multiply
120403 007xxx 142x07 03xxxx RPD Register Packed Divide
120403 011xxx 142x11 03xxxx RPCL Register Packed Compare Long
120403 012xxx 142x12 03xxxx RPMEL Register Packed Multiply Extensibly Long
120403 013xxx 142x13 03xxxx RPDEL Register Packed Divide Extensibly Long
120403 014xxx 142x14 03xxxx RPAL Register Packed Add Long
120403 015xxx 142x15 03xxxx RPSL Register Packed Subtract Long
120403 016xxx 142x16 03xxxx RPML Register Packed Multiply Long
120403 017xxx 142x17 03xxxx RPDL Register Packed Divide Long
120403 021xxx 142x21 03xxxx RCDC Register Compressed Decimal Compare
120403 022xxx 142x22 03xxxx RCDME Register Compressed Decimal Multiply Extensibly
120403 023xxx 142x23 03xxxx RCDDE Register Compressed Decimal Divide Extensibly
120403 024xxx 142x24 03xxxx RCDA Register Compressed Decimal Add
120403 025xxx 142x25 03xxxx RCDS Register Compressed Decimal Subtract
120403 026xxx 142x26 03xxxx RCDM Register Compressed Decimal Multiply
120403 027xxx 142x27 03xxxx RCDD Register Compressed Decimal Divide
120403 031xxx 142x31 03xxxx RCDCL Register Compressed Decimal Compare Long
120403 032xxx 142x32 03xxxx RCDMEL Register Compressed Decimal Multiply Extensibly Long
120403 033xxx 142x33 03xxxx RCDDEL Register Compressed Decimal Divide Extensibly Long
120403 034xxx 142x34 03xxxx RCDAL Register Compressed Decimal Add Long
120403 035xxx 142x35 03xxxx RCDSL Register Compressed Decimal Subtract Long
120403 036xxx 142x36 03xxxx RCDML Register Compressed Decimal Multiply Long
120403 037xxx 142x37 03xxxx RCDDL Register Compressed Decimal Divide Long
120403 040xxx 142x40 03xxxx SWMDE Swap Medium Decimal Exponent
120403 041xxx 142x41 03xxxx CMDE Compare Medium Decimal Exponent
120403 042xxx 142x42 03xxxx LMDE Load Medium Decimal Exponent
120403 043xxx 142x43 03xxxx STMDE Store Medium Decimal Exponent
120403 044xxx 142x44 03xxxx AMDE Add Medium Decimal Exponent
120403 045xxx 142x45 03xxxx SMDE Subtract Medium Decimal Exponent
120403 046xxx 142x46 03xxxx MMDE Multiply Medium Decimal Exponent
120403 047xxx 142x47 03xxxx DMDE Divide Medium Decimal Exponent
120403 052xxx 142x52 03xxxx LUMDE Load Unnormalized Medium Decimal Exponent
120403 053xxx 142x53 03xxxx STUMDE Store Unnormalized Medium Decimal Exponent
120403 054xxx 142x54 03xxxx AUMDE Add Unnormalized Medium Decimal Exponent
120403 055xxx 142x55 03xxxx SUMDE Subtract Unnormalized Medium Decimal Exponent
120403 056xxx 142x56 03xxxx MUMDE Multiply Unnormalized Medium Decimal Exponent
120403 057xxx 142x57 03xxxx DUMDE Divide Unnormalized Medium Decimal Exponent
120403 060xxx 142x60 03xxxx SWDDE Swap Double Decimal Exponent
120403 061xxx 142x61 03xxxx CDDE Compare Double Decimal Exponent
120403 062xxx 142x62 03xxxx LDDE Load Double Decimal Exponent
120403 063xxx 142x63 03xxxx STDDE Store Double Decimal Exponent
120403 064xxx 142x64 03xxxx ADDE Add Double Decimal Exponent
120403 065xxx 142x65 03xxxx SDDE Subtract Double Decimal Exponent
120403 066xxx 142x66 03xxxx MDDE Multiply Double Decimal Exponent
120403 067xxx 142x67 03xxxx DDDE Divide Double Decimal Exponent
120403 072xxx 142x72 03xxxx LUDDE Load Unnormalized Double Decimal Exponent
120403 073xxx 142x73 03xxxx STUDDE Store Unnormalized Double Decimal Exponent
120403 074xxx 142x74 03xxxx AUDDE Add Unnormalized Double Decimal Exponent
120403 075xxx 142x75 03xxxx SUDDE Subtract Unnormalized Double Decimal Exponent
120403 076xxx 142x76 03xxxx MUDDE Multiply Unnormalized Double Decimal Exponent
120403 077xxx 142x77 03xxxx DUDDE Divide Unnormalized Double Decimal Exponent
120404 054xxx 142x54 04xxxx AMDEH Add Medium Decimal Exponent Humanized
120404 055xxx 142x55 04xxxx SMDEH Subtract Medium Decimal Exponent Humanized
120404 056xxx 142x56 04xxxx MMDEH Multiply Medium Decimal Exponent Humanized
120404 057xxx 142x57 04xxxx DMDEH Divide Medium Decimal Exponent Humanized
120404 074xxx 142x74 04xxxx ADDEH Add Double Decimal Exponent Humanized
120404 075xxx 142x75 04xxxx SDDEH Subtract Double Decimal Exponent Humanized
120404 076xxx 142x76 04xxxx MDDEH Multiply Double Decimal Exponent Humanized
120404 077xxx 142x77 04xxxx DDDEH Divide Double Decimal Exponent Humanized
120405 000xxx 142x00 05xxxx SWFRC Swap Floating Register Compressed
120405 001xxx 142x01 05xxxx CFRC Compare Floating Register Compressed
120405 002xxx 142x02 05xxxx LFRC Load Floating Register Compressed
120405 003xxx 142x03 05xxxx STFRC Store Floating Register Compressed
120405 004xxx 142x04 05xxxx AFRC Add Floating Register Compressed
120405 005xxx 142x05 05xxxx SFRC Subtract Floating Register Compressed
120405 006xxx 142x06 05xxxx MFRC Multiply Floating Register Compressed
120405 007xxx 142x07 05xxxx DFRC Divide Floating Register Compressed
120405 012xxx 142x12 05xxxx LUFRC Load Unnormalized Floating Register Compressed
120405 013xxx 142x13 05xxxx STUFRC Store Unnormalized Floating Register Compressed
120405 014xxx 142x14 05xxxx AUFRC Add Unnormalized Floating Register Compressed
120405 015xxx 142x15 05xxxx SUFRC Subtract Unnormalized Floating Register Compressed
120405 016xxx 142x16 05xxxx MUFRC Multiply Unnormalized Floating Register Compressed
120405 017xxx 142x17 05xxxx DUFRC Divide Unnormalized Floating Register Compressed
120405 024xxx 142x24 05xxxx AFRCH Add Floating Register Compressed Humanized
120405 025xxx 142x25 05xxxx SFRCH Subtract Floating Register Compressed Humanized
120405 026xxx 142x26 05xxxx MFRCH Multiply Floating Register Compressed Humanized
120405 027xxx 142x27 05xxxx DFRCH Divide Floating Register Compressed Humanized
120405 040xxx 142x40 05xxxx SWDRC Swap Double Register Compressed
120405 041xxx 142x41 05xxxx CDRC Compare Double Register Compressed
120405 042xxx 142x42 05xxxx LDRC Load Double Register Compressed
120405 043xxx 142x43 05xxxx STDRC Store Double Register Compressed
120405 044xxx 142x44 05xxxx ADRC Add Double Register Compressed
120405 045xxx 142x45 05xxxx SDRC Subtract Double Register Compressed
120405 046xxx 142x46 05xxxx MDRC Multiply Double Register Compressed
120405 047xxx 142x47 05xxxx DDRC Divide Double Register Compressed
120405 052xxx 142x52 05xxxx LUDRC Load Unnormalized Double Register Compressed
120405 053xxx 142x53 05xxxx STUDRC Store Unnormalized Double Register Compressed
120405 054xxx 142x54 05xxxx AUDRC Add Unnormalized Double Register Compressed
120405 055xxx 142x55 05xxxx SUDRC Subtract Unnormalized Double Register Compressed
120405 056xxx 142x56 05xxxx MUDRC Multiply Unnormalized Double Register Compressed
120405 057xxx 142x67 05xxxx DUDRC Divide Unnormalized Double Register Compressed
120405 064xxx 142x64 05xxxx AFDCH Add Double Register Compressed Humanized
120405 065xxx 142x65 05xxxx SFDCH Subtract Double Register Compressed Humanized
120405 066xxx 142x66 05xxxx MFDCH Multiply Double Register Compressed Humanized
120405 067xxx 142x67 05xxxx DFDCH Divide Double Register Compressed Humanized
120406 000xxx 142x00 06xxxx SWQRC Swap Quad Register Compressed
120406 001xxx 142x01 06xxxx CQRC Compare Quad Register Compressed
120406 002xxx 142x02 06xxxx LQRC Load Quad Register Compressed
120406 003xxx 142x03 06xxxx STQRC Store Quad Register Compressed
120406 004xxx 142x04 06xxxx AQRC Add Quad Register Compressed
120406 005xxx 142x05 06xxxx SQRC Subtract Quad Register Compressed
120406 006xxx 142x06 06xxxx MQRC Multiply Quad Register Compressed
120406 007xxx 142x07 06xxxx DQRC Divide Quad Register Compressed
120406 012xxx 142x12 06xxxx LUQRC Load Unnormalized Quad Register Compressed
120406 013xxx 142x13 06xxxx STUQRC Store Unnormalized Quad Register Compressed
120406 014xxx 142x14 06xxxx AUQRC Add Unnormalized Quad Register Compressed
120406 015xxx 142x15 06xxxx SUQRC Subtract Unnormalized Quad Register Compressed
120406 016xxx 142x16 06xxxx MUQRC Multiply Unnormalized Quad Register Compressed
120406 017xxx 142x17 06xxxx DUQRC Divide Unnormalized Quad Register Compressed
120406 024xxx 142x24 06xxxx AFDCH Add Quad Register Compressed Humanized
120406 025xxx 142x25 06xxxx SFDCH Subtract Quad Register Compressed Humanized
120406 026xxx 142x26 06xxxx MFDCH Multiply Quad Register Compressed Humanized
120406 027xxx 142x27 06xxxx DFDCH Divide Quad Register Compressed Humanized
120406 040xxx 142x40 06xxxx SWNFRC Swap Numerical Floating Register Compressed
120406 041xxx 142x41 06xxxx CNFRC Compare Numerical Floating Register Compressed
120406 042xxx 142x42 06xxxx LNFRC Load Numerical Floating Register Compressed
120406 043xxx 142x43 06xxxx STNFRC Store Numerical Floating Register Compressed
120406 044xxx 142x44 06xxxx ANFRC Add Numerical Floating Register Compressed
120406 045xxx 142x45 06xxxx SNFRC Subtract Numerical Floating Register Compressed
120406 046xxx 142x46 06xxxx MNFRC Multiply Numerical Floating Register Compressed
120406 047xxx 142x47 06xxxx DNFRC Divide Numerical Floating Register Compressed
120406 050xxx 142x50 06xxxx SWNDRC Swap Numerical Double Register Compressed
120406 051xxx 142x51 06xxxx CNDRC Compare Numerical Double Register Compressed
120406 052xxx 142x52 06xxxx LNDRC Load Numerical Double Register Compressed
120406 053xxx 142x53 06xxxx STNDRC Store Numerical Double Register Compressed
120406 054xxx 142x54 06xxxx ANDRC Add Numerical Double Register Compressed
120406 055xxx 142x55 06xxxx SNDRC Subtract Numerical Double Register Compressed
120406 056xxx 142x56 06xxxx MNDRC Multiply Numerical Double Register Compressed
120406 057xxx 142x57 06xxxx DNDRC Divide Numerical Double Register Compressed
120406 060xxx 142x60 06xxxx SWNQRC Swap Numerical Quad Register Compressed
120406 061xxx 142x61 06xxxx CNQRC Compare Numerical Quad Register Compressed
120406 062xxx 142x62 06xxxx LNQRC Load Numerical Quad Register Compressed
120406 063xxx 142x63 06xxxx STNQRC Store Numerical Quad Register Compressed
120406 064xxx 142x64 06xxxx ANQRC Add Numerical Quad Register Compressed
120406 065xxx 142x65 06xxxx SNQRC Subtract Numerical Quad Register Compressed
120406 066xxx 142x66 06xxxx MNQRC Multiply Numerical Quad Register Compressed
120406 067xxx 142x67 06xxxx DNQRC Divide Numerical Quad Register Compressed
In this mode, the opcodes of the shift instructions are:
140xxx SHLB Shift Left Byte 141xxx SHRB Shift Right Byte 143xxx ASRB Arithmetic Shift Right Byte 144xxx ROLB Rotate Left Byte 145xxx RORB Rotate Right Byte 146xxx RLCB Rotate Left through Carry Byte 147xxx RRCB Rotate Right through Carry Byte 150xxx SHLH Shift Left Halfword 151xxx SHRH Shift Right Halfword 153xxx ASRH Arithmetic Shift Right Halfword 154xxx ROLH Rotate Left Halfword 155xxx RORH Rotate Right Halfword 156xxx RLCH Rotate Left through Carry Halfword 157xxx RRCH Rotate Right through Carry Halfword 160xxx SHL Shift Left 161xxx SHR Shift Right 163xxx ASR Arithmetic Shift Right 164xxx ROL Rotate Left 165xxx ROR Rotate Right 166xxx RLC Rotate Left through Carry 167xxx RRC Rotate Right through Carry 170xxx SHLL Shift Left Long 171xxx SHRL Shift Right Long 173xxx ASRL Arithmetic Shift Right Long 174xxx ROLL Rotate Left Long 175xxx RORL Rotate Right Long 176xxx RLCL Rotate Left through Carry Long 177xxx RRCL Rotate Right through Carry Long
The unused operand 2 for a shift instruction is used to form 16-bit prefixes which extend the instruction repertoire. Shown in the diagram is the simplest extension provided, in which the opcode field is extended to 12 bits, but the addressing modes are essentially unchanged, except for allowing all eight registers to be the destination of a scratchpad instruction. The 12-bit opcodes are defined to be the same as the 8-bit opcodes used in full opcode mode, with nonzero values of the first four bits reserved for future expansion.
Other prefix values will allow additional addressing modes, particularly for vector operations, and will prefix such operate instructions as the conditional jump instructions or the packed decimal arithmetic instructions.
Among the instructions which remain to be defined, the conditional jump and subroutine jump instructions are relatively common instructions. Fortunately, there is sufficient opcode space among the unused shift instructions so that lengthening them can be avoided. This is not also true for the branch instructions; but the long branch instructions, in which the case where the base register is zero is defined as indicating a branch instruction with a 16-bit signed displacement, remain available.
Thus, the opcodes for these instructions are:
152xxx JMS Jump to Subroutine 152xx0 BRS Branch to Subroutine 1621xx JL Jump if Low 1622xx JE Jump if Equal 1623xx JLE Jump if Low or Equal 1624xx JH Jump if High 1625xx JNE Jump if Not Equal 1626xx JHE Jump if High or Equal 1627xx JNV Jump if No Overflow 1720xx JV Jump if Overflow 1722xx JC Jump if Carry 1723xx JNC Jump if No Carry 1727xx JMP Jump 1621x0 LBL Long Branch if Low 1622x0 LBE Long Branch if Equal 1623x0 LBLE Long Branch if Low or Equal 1624x0 LBH Long Branch if High 1625x0 LBNE Long Branch if Not Equal 1626x0 LBHE Long Branch if High or Equal 1627x0 LBNV Long Branch if No Overflow 1720x0 LBV Long Branch if Overflow 1722x0 LBC Long Branch if Carry 1723x0 LBNC Long Branch if No Carry 1727x0 LBRA Long Branch
If indexed addressing is used in a jump or long branch instruction, the instruction does not jump to the memory location at the effective address, but instead to the location whose address it contains. This addressing mode, post-indexed indirect addressing, allows branching to one of several locations in a list. This also applies to the JMS and BRS instructions.
For the long vector instructions, it will be necessary to reduce the length of the opcode field from 12 bits to 9 bits, still more than the 8 bits currently used, and to use a considerable proportion of the remaining opcode space available for prefixes.
Providing the operate instructions with a 16-bit prefix ensures that ample opcode space will remain for the long vector and extended operate instructions also provided in this mode. First, the character and packed decimal instructions are shown:
and then the remaining operate instructions:
Although advanced compound mode was designed so as to allow efficient and full access to the entire architecture without any further requirement for switching to other instruction modes, some choice and flexibility may still be felt desirable.
Thus, where convenient and efficient access to 64-bit fixed point, and 48-bit and 128-bit floating point outweighs the added compactness provided by the 16-bit scratchpad instructions, a modification of this mode that uses the same conventional memory reference instructions as normal mode is presented:
This mode attempts to combine the benefits of modified normal mode with having short memory-reference instructions for alternate types as well. This is done by moving to six-bit opcodes for the memory-reference instructions whose format resembles that of normal mode, and then having a second set of six-bit opcodes for additional types, giving the supplementary memory reference instructions. The opcodes involved are listed in the table above; unfortunately, opcode space is sufficiently limited that only the unnormalized floating-point instructions benefit from this measure, which works by limiting indexed memory reference instructions to register 0 as their destination register.
Thus, the first group of memory-reference instructions uses the default 6-bit opcode set, providing support for byte, halfword, and word fixed-point types, and for normalized floating and double operations; the long fixed-point type, unnormalized floating and double operations, as well as normalized and unnormalized medium and quad operations are in the supplementary set.
Due to the interconnectedness of those two sets of opcodes, opcode translation is not provided in this mode.
Then, there is a third set of opcodes: sixteen opcodes are available for the auxilliary memory reference instructions. As this is enough only to select an opcode for a single type of operand, a five-bit field in the Program Status Block, the last three bits of which having already been used to indicate the type of operands in the plain scratchpad modes and in the stack modes, is used to indicate which type of operands is handled by these instructions.
In this mode, another limitation of these modes, arising from adding 16 bits to the length to all the operate instructions except the shift instructions, is corrected: the conditional branch instructions can once again have 16-bit opcodes, and they are:
1361xx BL Branch if Low 1362xx BE Branch if Equal 1363xx BLE Branch if Low or Equal 1364xx BH Branch if High 1365xx BNE Branch if Not Equal 1366xx BHE Branch if High or Equal 1367xx BNV Branch if No Overflow 1370xx BV Branch if Overflow 1372xx BC Branch if Carry 1373xx BNC Branch if No Carry 1677xx BRA Branch
On the other hand, if compactness in the representation of programs is desirable, while the 16-bit scratchpad operations help to provide this compactness, the ultimate in compactness is to be found by including up to three operations in each 16-bit halfword through a stack mode.
This mode, however, does have the liability in high-performance implementations that successive operations usually will depend on the preceding operation. This means that multiple concurrent threads will be required to avoid waste of computing resources in a pipelined implementation.
The format of instructions in this mode is depicted below:
The stack operations in this mode have the following opcodes:
00000 NOP no operation
00001 00nnn TYPE switch to operating on values of type nnn:
000 byte 100 medium
001 halfword 101 floating
010 integer 110 double
011 long 111 quad
00010 DUP append an extra copy of the current top item
on the stack to the top of the stack
00011 DROP discard the top item on the stack
00100 ADD replace the top two items on the stack with
one item containing their sum
00101 SUB
00110 MUL
00111 DIV
01000 AND ADDU AND for fixed-point values, unnormalized ADD for
floating-point ones
01001 OR SUBU
01010 XOR MULU
01011 DIVU
01100 SWAP exchange the top two items on the stack
01101 ROT
11110 0nnn0 PUSHR append the value in register nnn to the top of
the stack
11110 1bbba aaaaa aaaaa aaaaa
PUSH append the value in memory location aaaaaaaaaaaaaaaa
plus the contents of base register bbb to the top of
the stack
11110 0bbb1 0xxxa aaaaa aaaaa aaaaa
PUSH append the value in memory location aaaaaaaaaaaaaaaa
plus the contents of base register bbb plus the contents
of arithmetic-index register xxx to the top of the stack
11111 0nnn0 POPR remove the top item on the stack, and place it
in register nnn
11111 1bbba aaaaa aaaaa aaaaa
POP remove the top item on the stack, and place it in memory
location aaaaaaaaaaaaaaaa plus the contents of base register
bbb
11111 0bbb1 0xxxa aaaaa aaaaa aaaaa
POP remove the top item on the stack, and place it in memory
location aaaaaaaaaaaaaaaa plus the contents of base register
bbb plus the contents of arithmetic-index register xxx
In this mode, there are only two stacks; one for integers and one for floating-point numbers, in the appropriate set of supplementary registers. Base register zero contains the six-bit pointer for each, as a number equal to 256 times the fixed-point pointer value plus the floating-point pointer value.
Aside from the fact that the field used to specify an index register usually contains only a zero, indicating that indexing is not selected, another problem with normal mode is that if a program deals with several arrays larger than 64 kilobytes in size, even if the same base register used to access one such array can also access some shorter items ahead of it, each base register can point to at most one large array.
This addressing mode attempts to deal with both of these problems, and thus the full opcode instructions, which in the other modes remain similar to normal mode, are also changed. Here, when indexing is used, a base register is not needed, because a full absolute 32-bit address is used to point to the array. However, general registers 4 through 7 can also be used as index registers for conventional indexed access within the domains of base registers as well.
This provides room for scratchpad instructions referencing the supplementary registers, but always having register 0 as their destination, as 16-bit normal opcode instructions as well.
Large Array Mode deals with the problem of allowing a program to refer to more than eight local arrays larger than 64 kilobytes in size at one time. However, it does not address handling more than eight large arrays at once where the addresses of these arrays are not constant, but are instead passed to a subroutine as parameters.
Pointer Page Mode, with instruction formats as illustrated below:
omits the 16-bit instructions that perform operations between a register and a supplementary register, to free up opcode space for addressing modes that do deal with this issue.
Registers 1 through 7 of the set of eight scratchpad registers are each used to point to an expanse of memory containing 4,096 address constants. Thus, the address displacements in Pointer Page and Pointer Page Post-Indexed formats are in units of 32 bits (or 64 bits, if 64-bit addressing is enabled). An instruction in Pointer Page format allows a pointer to be accessed; an instruction in Pointer Page Post-Indexed format uses the pointer to indicate the starting point of an array, the contents of which are accessed by a byte displacement in the general register from 1 through 7 indicated as that instruction's index register.
Scratchpad register 0, except for its least significant 15 bits, is used to indicate a 32 kilobyte area of memory, aligned on a 32 kilobyte boundary, which is native to the current program segment. Own Page and Own Page Indexed format instructions therefore allow relocatable programs whose relocatability is limited to even 32 kilobyte boundaries to perform memory reference instructions without the additional overhead of adding a base register address, since instead only the concatenation of bits is required.
This mode attempts to approach the efficiency, as regards code density, of minicomputer architectures.
Using a six bit opcode field, which allows 8, 16, and 32 bit integer types and 32 and 64 bit floating-point types with the most common operations, and the destination register fixed at register zero, enough space is left in a 16-bit instruction word to indicate an address within a 512-byte memory area. This is the short memory reference type of instruction.
Base register zero (not scratchpad register zero, despite the use of the scratchpad registers as base registers with the basic types of memory-reference instructions in this mode) is used to point to this area.
For the other basic memory-reference instructions, the opcode field is seven bits in length, with its contents unrestricted. This allows the use of the unnormalized floating-point instructions without increasing the length of the instruction.
However, the remaining opcode space is somewhat constrained. The register-to-register instructions are not affected adversely by this.
But in the case of memory-reference instructions, the area of memory pointed to by the contents of any of base registers 1 through 7 is reduced to 32 K bytes from 64 K bytes compared with most addressing modes. In addition, a choice has to be made between specifying the destination register of a memory-reference instruction, or assuming the destination register to be register zero in order to allow indexing. As a result, the scratchpad registers are used as base registers with them rather than the normal base registers.
Also, while general register zero is not used as an index register, and the normal base register zero is not used as a base register with the addressing modes involving them, scratchpad register zero, when indicated in these addressing modes, is also used as a base register rather than indicating absolute addressing.
The full opcode modes are similar to those with most of the other modes on this page, and, as their address fields are 16 bits in length, they, along with the operate instructions, use the normal base registers.
Due to the fact that the base register field and the address field are not contiguous in the normal-length memory-reference instructions, initially I hesitated in specifying a direct cache version of this mode, but I have relented.
The instruction formats in this mode have the form:
This mode is identical to Short Memory Reference Mode except that the normal-length indexed instructions now allow any of registers 0 to 3 to be the destination register; the index register must be one of arithmetic/index registers 4 through 7, and only scratchpad registers 0 through 3 may be used as base registers.
This mode also does not have a direct cache version; not only is the base register field not contiguous with the address field, but furthermore, it now varies in length depending on whether indexing is present.