This page deals with short page mode, and the substantially identical register short page mode, which allow vector and scratchpad operations to be combined with normal memory-reference instructions while retaining full seven-bit instruction opcodes, by shortening the displacement field in the instruction to twelve bits from sixteen, and also with four modes that allow additional features of the architecture to be accessed by going to six-bit opcodes as well.
Short page mode follows the IBM 360 by changing the size of the areas to which base registers point from 65,536 bytes to 4,096 bytes, thereby increasing the available opcode space so as to allow more of the computer's features to be available at one time. In this mode, memory-reference instructions have the following formats:
and the additional instructions have almost the same format as in normal mode, except that their address fields are also modified in the same fashion, which also creates room for a few additional instructions, the character, packed decimal, and related instructions:
and the other special instructions:
and the resulting opcodes are now:
140xxx x02xxx LBSV Load Byte Short Vector 140xxx x03xxx STBSV Store Byte Short Vector 140xxx x04xxx ABSV Add Byte Short Vector 140xxx x05xxx SBSV Subtract Byte Short Vector 140xxx x10xxx NBSV AND Byte Short Vector 140xxx x11xxx OBSV OR Byte Short Vector 140xxx x12xxx XBSV XOR Byte Short Vector 140xxx x13xxx SWBSV Swap Byte Short Vector 140xxx 0342xx LSVM Load Short Vector Multiple 140xxx 0343xx STSVM Store Short Vector Multiple 140xxx x15xxx SMBPB Set Mask Bit if Positive Byte 140xxx x16xxx SMBZB Set Mask Bit if Zero Byte 140xxx x17xxx SMBNB Set Mask Bit if Negative Byte 141xxx x02xxx LHSV Load Halfword Short Vector 141xxx x03xxx STHSV Store Halfword Short Vector 141xxx x04xxx AHSV Add Halfword Short Vector 141xxx x05xxx SHSV Subtract Halfword Short Vector 141xxx x06xxx MHSV Multiply Halfword Short Vector 141xxx x07xxx DHSV Divide Halfword Short Vector 141xxx x10xxx NHSV AND Halfword Short Vector 141xxx x11xxx OHSV OR Halfword Short Vector 141xxx x12xxx XHSV XOR Halfword Short Vector 141xxx x13xxx SWHSV Swap Halfword Short Vector 141xxx x15xxx SMBPH Set Mask Bit if Positive Halfword 141xxx x16xxx SMBZH Set Mask Bit if Zero Halfword 141xxx x17xxx SMBNH Set Mask Bit if Negative Halfword 142xxx x02xxx LSV Load Short Vector 142xxx x03xxx STSV Store Short Vector 142xxx x04xxx ASV Add Short Vector 142xxx x05xxx SSV Subtract Short Vector 142xxx x06xxx MSV Multiply Short Vector 142xxx x07xxx DSV Divide Short Vector 142xxx x10xxx NSV AND Short Vector 142xxx x11xxx OSV OR Short Vector 142xxx x12xxx XSV XOR Short Vector 142xxx x13xxx SWSV Swap Short Vector 142xxx x15xxx SMBPB Set Mask Bit if Positive 142xxx x16xxx SMBZB Set Mask Bit if Zero 142xxx x17xxx SMBNB Set Mask Bit if Negative 143xxx x02xxx LLSV Load Long Short Vector 143xxx x03xxx STLSV Store Long Short Vector 143xxx x04xxx ALSV Add Long Short Vector 143xxx x05xxx SLSV Subtract Long Short Vector 143xxx x06xxx MLSV Multiply Long Short Vector 143xxx x07xxx DLSV Divide Long Short Vector 143xxx x10xxx NLSV AND Long Short Vector 143xxx x11xxx OLSV OR Long Short Vector 143xxx x12xxx XLSV XOR Long Short Vector 143xxx x13xxx SWLSV Swap Long Short Vector 143xxx x15xxx SMBPL Set Mask Bit if Positive Long 143xxx x16xxx SMBZL Set Mask Bit if Zero Long 143xxx x17xxx SMBNL Set Mask Bit if Negative Long 145xxx x02xxx LFSV Load Floating Short Vector 145xxx x03xxx STFSV Store Floating Short Vector 145xxx x04xxx AFSV Add Floating Short Vector 145xxx x05xxx SFSV Subtract Floating Short Vector 145xxx x06xxx MFSV Multiply Floating Short Vector 145xxx x07xxx DFSV Divide Floating Short Vector 145xxx x15xxx SMBPF Set Mask Bit if Positive Floating 145xxx x16xxx SMBZF Set Mask Bit if Zero Floating 145xxx x17xxx SMBNF Set Mask Bit if Negative Floating 146xxx x02xxx LDSV Load Double Short Vector 146xxx x03xxx STDSV Store Double Short Vector 146xxx x04xxx ADSV Add Double Short Vector 146xxx x05xxx SDSV Subtract Double Short Vector 146xxx x06xxx MDSV Multiply Double Short Vector 146xxx x07xxx DDSV Divide Double Short Vector 146xxx x15xxx SMBPD Set Mask Bit if Positive Double 146xxx x16xxx SMBZD Set Mask Bit if Zero Double 146xxx x17xxx SMBND Set Mask Bit if Negative Double 147xxx x02xxx LQSV Load Quad Short Vector 147xxx x03xxx STQSV Store Quad Short Vector 147xxx x04xxx AQSV Add Quad Short Vector 147xxx x05xxx SQSV Subtract Quad Short Vector 147xxx x06xxx MQSV Multiply Quad Short Vector 147xxx x07xxx DQSV Divide Quad Short Vector 147xxx x15xxx SMBPQ Set Mask Bit if Positive Quad 147xxx x16xxx SMBZQ Set Mask Bit if Zero Quad 147xxx x17xxx SMBNQ Set Mask Bit if Negative Quad 140x4x 0000x0 MESTP Multiply Extensibly and Store Packed 141x4x 0000x0 CP Compare Packed 142x4x 0000x0 MVP Move Packed 143x4x 0000x0 DSTRP Divide and Store Remainder 144x4x 0000x0 AP Add Packed 145x4x 0000x0 SP Subtract Packed 146x4x 0000x0 MP Multiply Packed 147x4x 0000x0 DP Divide Packed 142x4x 0001x0 P Pack 143x4x 0001x0 U Unpack 141x4x 0400x0 CC Compare Character 142x4x 0400x0 MVC Move Character 14040x 04x1xx CVPB Convert Packed to Byte 14042x 04x1xx CVBP Convert Byte to Packed 14044x 04x1xx CVPH Convert Packed to Halfword 14046x 04x1xx CVHP Convert Halfword to Packed 14050x 04x1xx CVPW Convert Packed to Word 14052x 04x1xx CVWP Convert Word to Packed 14054x 04x1xx CVPL Convert Packed to Long 14056x 04x1xx CVLP Convert Long to Packed 14060x 04x1xx CVPM Convert Packed to Medium 14062x 04x1xx CVMP Convert Medium to Packed 14064x 04x1xx CVPF Convert Packed to Floating 14066x 04x1xx CVFP Convert Floating to Packed 14070x 04x1xx CVPD Convert Packed to Double 14072x 04x1xx CVDP Convert Double to Packed 14074x 04x1xx CVPQ Convert Packed to Quad 14076x 04x1xx CVQP Convert Quad to Packed 1404xx 04x2x0 CV Convert 1414xx 04x2x0 CVR Convert Reversed 1434xx 04x2x0 CVRI Convert Reversed Incomplete 1444xx 04x2x0 CVBF Convert Bit Field 1404xx 04x3x0 DCV Displaced Convert 1414xx 04x3x0 DCVR Displaced Convert Reversed 1434xx 04x3x0 DCVRI Displaced Convert Reversed Incomplete 1444xx 04x3x0 DCVBF Displaced Convert Bit Field 140x4x 10x0x0 TBH Translate Byte to Halfword 141x4x 10x0x0 TTHB Table Translate Halfword to Byte 142x4x 10x0x0 T Translate 143x4x 10x0x0 TH Translate Halfword 144x4x 10x0x0 FMT Format 145x4x 10x0x0 SC Scan 146x4x 10x0x0 DET Define Extended Translate 147x4x 10x0x0 EET Execute Extended Translate 152xx0 LM Load Multiple 153xx0 STM Store Multiple 152xx1 LMQ Load Multiple Quad 153xx1 STMQ Store Multiple Quad 152xx4 LMBR Load Multiple Base Registers 153xx4 STMBR Store Multiple Base Registers 152xx5 LMSB Load Multiple Scratchpad Base 153xx5 STMSB Store Multiple Scratchpad Base 152xx6 LMPSB Load Multiple Pointer Scratchpad Base 153xx6 STMPSB Store Multiple Pointer Scratchpad Base 152xx7 LMASB Load Multiple Array Scratchpad Base 153xx7 STMASB Store Multiple Array Scratchpad Base 161xx0 JMS Jump to Subroutine 1620xx SLBR Supplementary Load Base Register 1630xx SSTBR Supplementary Store Base Register 1625xx SLSB Supplementary Load Scratchpad Base 1635xx SSSB Supplementary Store Scratchpad Base 1626xx SLPSB Supplementary Load Pointer Scratchpad Base 1636xx SSPSB Supplementary Store Pointer Scratchpad Base 1627xx SLASB Supplementary Load Array Scratchpad Base 1637xx SSASB Supplementary Store Array Scratchpad Base 1661x6 JL Jump if Low 1662x6 JE Jump if Equal 1663x6 JLE Jump if Low or Equal 1664x6 JH Jump if High 1665x6 JNE Jump if Not Equal 1666x6 JHE Jump if High or Equal 1667x6 JNV Jump if No Overflow 1670x6 JV Jump if Overflow 1672x6 JC Jump if Carry 1673x6 JNC Jump if No Carry 1677x6 JMP Jump 166xx7 JXH Jump if Index High 167xx7 JXLE Jump if Index Low or Equal 17000x SHLB Shift Left Byte 17001x SHRB Shift Right Byte 17003x ASRB Arithmetic Shift Right Byte 17004x ROLB Rotate Left Byte 17005x RORB Rotate Right Byte 17006x RLCB Rotate Left through Carry Byte 17007x RRCB Rotate Right through Carry Byte 17100x SHLH Shift Left Halfword 17101x SHRH Shift Right Halfword 17103x ASRH Arithmetic Shift Right Halfword 17104x ROLH Rotate Left Halfword 17105x RORH Rotate Right Halfword 17106x RLCH Rotate Left through Carry Halfword 17107x RRCH Rotate Right through Carry Halfword 17200x SHL Shift Left 17201x SHR Shift Right 17203x ASR Arithmetic Shift Right 17204x ROL Rotate Left 17205x ROR Rotate Right 17206x RLC Rotate Left through Carry 17207x RRC Rotate Right through Carry 17300x SHLL Shift Left Long 17301x SHRL Shift Right Long 17303x ASRL Arithmetic Shift Right Long 17304x ROLL Rotate Left Long 17305x RORL Rotate Right Long 17306x RLCL Rotate Left through Carry Long 17307x RRCL Rotate Right through Carry Long
The additional opcode space made available by moving the specification of the base register into the address portion of the instruction allows all the data types of normal mode to be used, in combination with vector instructions and stateless scratchpad instructions, although here the plain scratchpad instructions must also only have register 0 as their destination register. Also, an additional bit in each address is used to indicate indirect addressing; an indirect address points to a 32-bit address, not a 16-bit address constant in the same form as the address field of an instruction, so multiple-level indirection is not available.
Also, note that when indexing is present along with indirection, the result is pre-indexed indirect addressing, so a pointer is selected from a list rather than being treated as a pointer to an array. This doesn't apply to the scratchpad instructions, which still provide the more useful indirect post-indexed addressing mode.
Also, the supplementary memory-reference instructions, while they do not permit all the addressing modes provided with normal memory-reference instructions, now do permit indexed addressing in this mode.
Because the base register is now moved out of the opcode portion of the instruction, and is instead in the address portion, a register to register short vector instruction has to be indicated explicitly, rather than by indicating register zero as the base register.
As with register scratchpad mode versus stateless scratchpad mode, register short page mode has the same instruction formats as short page mode, but instead of using one of sixty-four operands in memory in an area indicated by one of the scratchpad registers, the scratchpad instructions instead reference one of the supplementary registers.
This mode combines the use of short displacements, to make vector and scratchpad instructions available, with the use of opcode translation to make a short form of the shift instructions available. The memory-reference instructions in this mode, therefore, have the form:
and the short format shift instructions are as depicted previously:
This mode uses the supplementary registers instead of memory areas pointed to by the scratchpad registers for the scratchpad instructions, and therefore requires the use of the scratchpad format of the operate instructions as well, to provide the opcode space these operations require, but is otherwise identical to Short Page Short Shift mode.
Instructions in this mode have the form:
Here, instead of the short form of the shift instructions, what is made available by moving to six-bit opcodes is the ability to place two instructions in a single 16-bit halfword as provided with conensed mode. Also, the scratchpad instructions available in this mode, instead of being like those of the stateless scratchpad mode, are similar to those of stateful scratchpad mode, except that even the instructions without indirection or indexing may have only register 0 as their destination, as is true for the scratchpad instructions similar to those of the stateless scratchpad mode included in the other modes on this page.
Note that this means that in this mode, both a 16-bit substitute for a memory-reference instruction, and a two-per-word substitute for a register-to-register operation, are available.
Mutable Short Page Condensed Mode, Plain Stateful Short Page Condensed Mode, and Plain Mutable Short Page Condensed Mode
As with stateful scratchpad mode, this mode also has mutable, plain stateful, and plain mutable versions. In the mutable versions, the types in use are changed by memory-reference instructions that specify a type; in the plain versions, instead of it being possible for a floating-point type and a fixed-point type to be active at once, the floating-point types have sixteen basic operations, the unnormalized floating-point operations being included.
This mode provides the extended operate instructions instead of the short form of the shift instructions, but is otherwise identical to Short Page Short Shift mode.
In this mode, the extended operate instructions have the form:
This mode uses the supplementary registers instead of memory areas pointed to by the scratchpad registers for the scratchpad instructions, and is otherwise identical to Short Page Extended Operate mode.
The format of memory reference instructions in this mode is:
Here, scratchpad instructions are not provided, and instead the additional opcode space provided through the use of short pages is used to allow an eight-bit opcode field.
This allows the additional types to be referenced even by indexed instructions, unlike the case for Full Opcode Mode, previously described, and the possible opcodes are the same as for that mode.
This mode is identical to Short Page Full Opcode Mode, except that the vector operations are omitted, and their opcode space, that of the instructions beginning with the bits 10, is used instead for the short form of the shift instructions.
In this mode, the memory-reference instructions have this format:
Here, the eight scratchpad registers are used to point to areas in memory 512 bytes in length, and 16-bit operations are available with the following opcodes:
10xxxx LPSP Load Primary Scratchpad 11xxxx STPSP Store Primary Scratchpad 12xxxx LSSP Load Secondary Scratchpad 13xxxx STSSP Store Secondary Scratchpad
These instructions load to register 0, or store from register 0, of the appropriate type, operands whose length is determined by the current primary or secondary scratchpad type, as set by the SETPT and SETST instructions. As there is no overlap between opcodes for the primary and secondary type, the two types are fully independent in this mode.
This mode allows memory-reference instructions that match the register-to-register operations in length by limiting them to one destination register, two possible types, and by limiting them to loads and stores without indexing; this last limitation follows the model adopted for RISC computing, but the mode also includes conventional memory-reference instructions which are longer than 16 bits in length.
As well, since scratchpad register 0 is not used as a base register in this mode, additional opcode space is available for alternate memory-reference instructions. Indexed versions of these instructions are not offered; the register-to-register versions operate on all eight of the scratchpad, pointer scratchpad, or array scratchpad registers as their destination registers, and can have arithmetic/index registers 1, 2, or 3 as their source registers. The opcodes of these instructions are as follows, and they are shorter forms of some of the instructions which are prefixed by 173701:
0x000x SWBR Swap Base Register 0x001x CBR Compare Base Register 0x002x LBR Load Base Register 0x003x STBR Store Base Register 0x004x ABR Add Base Register 0x005x SBR Subtract Base Register 0x012x LBRA Load Base Register with Address 0x013x XBR XOR Base Register 0x014x NBR AND Base Register 0x015x OBR OR Base Register 0x020x SWSB Swap Scratchpad Base 0x021x CSB Compare Scratchpad Base 0x022x LSB Load Scratchpad Base 0x023x STSB Store Scratchpad Base 0x024x ASB Add Scratchpad Base 0x025x SSB Subtract Scratchpad Base 0x032x LSBA Load Scratchpad Base with Address 0x033x XSB XOR Scratchpad Base 0x034x NSB AND Scratchpad Base 0x035x OSB OR Scratchpad Base 0x040x SWPSB Swap Pointer Scratchpad Base 0x041x CPSB Compare Pointer Scratchpad Base 0x042x LPSB Load Pointer Scratchpad Base 0x043x STPSB Store Pointer Scratchpad Base 0x044x APSB Add Pointer Scratchpad Base 0x045x SPSB Subtract Pointer Scratchpad Base 0x052x LPSBA Load Pointer Scratchpad Base with Address 0x053x XPSB XOR Pointer Scratchpad Base 0x054x NPSB AND Pointer Scratchpad Base 0x055x OPSB OR Pointer Scratchpad Base 0x060x SWASB Swap Array Scratchpad Base 0x061x CASB Compare Array Scratchpad Base 0x062x LASB Load Array Scratchpad Base 0x063x STASB Store Array Scratchpad Base 0x064x AASB Add Array Scratchpad Base 0x065x SASB Subtract Array Scratchpad Base 0x072x LASBA Load Array Scratchpad Base with Address 0x073x XASB XOR Array Scratchpad Base 0x074x NASB AND Array Scratchpad Base 0x075x OASB OR Array Scratchpad Base
Also note that while, in this mode, types such as register packed decimal, decimal exponent floating-point, and simple floating cannot be selected as either the primary or secondary type for the load-store instructions, since full opcode memory reference instructions are available in addition to the full opcode register-to-register instructions, these types are still fully usable.
In this mode, the memory reference instructions have this form:
Here, six-bit opcode translation is used with the full memory-reference instructions, and they are restricted to using arithmetic/index registers 1, 2, and 3 as index registers. Only one type is used with the condensed instructions and the load/store instructions, selected in the same manner as for the plain scratchpad modes. Also, the load/store instructions can only use base registers 1, 2, and 3.
This allows normal register-to-register and memory reference instructions, in addition to both instructions that place a pair of register-to-register operations on the selected type, and with register zero as their destination operand (note that the register to register store operation is meaningful in this case), in a single 16-bit halfword, and load/store instructions that use the same 4,096-byte areas in memory, and three of the same base registers, as the regular short page memory-reference instructions, which also take up only a single 16-bit halfword.
As with the load/store instructions in short page compact mode, the destination register of these instructions is always register zero of the appropriate type, and their opcodes are:
00xxxx LSP Load Scratchpad 01xxxx STSP Store Scratchpad
Also allowed is a modified form of short shift instruction; unlike the regular shift instruction, which is still available as an operate instruction, and the short shift instruction in the short shift modes, these instructions can act only on register 0, and they have the operands:
010xx4 RZSHLB Register Zero Shift Left Byte 011xx4 RZSHRB Register Zero Shift Right Byte 013xx4 RZASRB Register Zero Arithmetic Shift Right Byte 014xx4 RZROLB Register Zero Rotate Left Byte 015xx4 RZRORB Register Zero Rotate Right Byte 016xx4 RZRLCB Register Zero Rotate Left through Carry Byte 017xx4 RZRRCB Register Zero Rotate Right through Carry Byte 010xx5 RZSHLH Register Zero Shift Left Halfword 011xx5 RZSHRH Register Zero Shift Right Halfword 013xx5 RZASRH Register Zero Arithmetic Shift Right Halfword 014xx5 RZROLH Register Zero Rotate Left Halfword 015xx5 RZRORH Register Zero Rotate Right Halfword 016xx5 RZRLCH Register Zero Rotate Left through Carry Halfword 017xx5 RZRRCH Register Zero Rotate Right through Carry Halfword 010xx6 RZSHL Register Zero Shift Left 011xx6 RZSHR Register Zero Shift Right 013xx6 RZASR Register Zero Arithmetic Shift Right 014xx6 RZROL Register Zero Rotate Left 015xx6 RZROR Register Zero Rotate Right 016xx6 RZRLC Register Zero Rotate Left through Carry 017xx6 RZRRC Register Zero Rotate Right through Carry 010xx7 RZSHLL Register Zero Shift Left Long 011xxx RZSHRL Register Zero Shift Right Long 013xx7 RZASRL Register Zero Arithmetic Shift Right Long 014xx7 RZROLL Register Zero Rotate Left Long 015xx7 RZRORL Register Zero Rotate Right Long 016xx7 RZRLCL Register Zero Rotate Left through Carry Long 017xx7 RZRRCL Register Zero Rotate Right through Carry Long
Finally, there is also a 16-bit address calculation instruction,
012xx4 CA Calculate Addresswhich takes the value in one of the eight base registers, adds to it the value in one of the eight arithmetic/index registers, and stores the result in one of the first four base registers. Although this duplicates the function of indexed addressing to some extent, it allows multiple references to the same array element to be made without adding the index again.
In these modes, the form of a 16-bit address field is modified. Instead of consisting of an indirect bit, followed by a three-bit base register specification, and then a 12-bit displacement, the first bit functions in a manner similar to that of the selector bit used in the Philco 2000 computers, at least according to one account. If the first bit is a zero, a 15-bit displacement follows it, to which is added the contents of base/address register zero; if the first bit is a one, then the next three bits indicate a base/address register, and are followed by a 12-bit displacement. Thus, while base/address registers 1 through 7 still point to 4,096-byte pages, base/address register 0 points to a 32,768-byte page.
In the case of Philco 2000 computer, the field that could be present or not indicated an index register; since indexing shortened the displacement field, however, an index register had to take on the duty of a base register as well, even though this was only needed when indexing was desired.
Many of the short page modes make use of all the scratchpad registers. But those that do not, or compact mode, which only uses the first set of scratchpad registers, can be modified in another way to permit the use of larger pages.
In these modes, if the first bit of an address halfword is set, the three-bit base register field refers to one of the array scrachpad registers, and the length of the address field is increased by 16 bits, to permit a 28-bit displacement to be used. The effect of this is similar to that of the 28/32-bit displacement bit in the Program Status Block, but here two different sizes of page are available in the same program, with a different set of registers pointing to pages of the appropriate size.