To provide additional addressing modes which allow more compact instructions to be used, four other modes of operation are defined. As well, a fifth mode, including a portion of the features of register scratchpad mode, and also including features from modes described on previous pages to permit more compact instruction encoding is described here.
Three of these modes make use of addresses in the three banks of scratchpad registers.
Which of the eight registers in one of those banks is used in an instruction is not specified by a field in the instruction, but instead depends on the type of its operands:
000 Byte 001 Halfword 010 Integer 011 Long 100 Medium 101 Floating 110 Double 111 Quad
The different banks of eight registers support different addressing modes.
Each scratchpad register points to an area of 64 (or, in stateful and mutable scratchpad modes, 256) data elements of the appropriate type. Thus, the scratchpad registers support direct memory addressing, allowing program modules to reference 64 simple variables in this mode.
The scratchpad pointer registers point to areas of 64 (or, in stateful and mutable scratchpad modes, 256) addresses (normally 32 bits long, unless 64-bit addressing is enabled) which point to values of the appropriate data type. Thus, the scratchpad pointer registers support indirect memory addressing, allowing program modules to reference up to 64 (or 256) simple variables passed to them as parameters.
The array scratchpad registers also point to areas of 64 or 256 addresses. When these registers are used, a field in the instruction has indicated that accumulator/index register 1, 2, or 3 is used with these addresses in indirect post-indexed addressing. Thus, the array scratchpad registers allow program modules to reference up to 64 or 256 arrays, and the size of these arrays can be up to 4,294,967,296 bytes each, determined by the 32-bit size of the accumulator/index registers.
The intent of the scratchpad modes is to make it possible to meet the usual memory reference requirements of typical programs without having to have a large proportion of instructions that are 32 bits long.
Register scratchpad mode still uses the array scratchpad registers to point to arrays in memory, and the scratchpad pointer registers for indirect memory references, but instead of using the scratchpad registers to point to an area in memory containing 64 data values, it uses the 64 supplementary registers for simple operands.
The formats used in these modes for memory-reference instructions are shown below:
For both stateless and register scratchpad mode:
and both stateful and mutable scratchpad mode:
The stateless scratchpad mode and the register scratchpad mode restrict the availability of the different operand types with which the machine can work somewhat in order to offer additional addressing modes that allow the use of shorter instructions, reflecting the fact that most programs can be divided into routines which use only a limited number of variables. Three different scratchpad registers for each variable type handle a routine's internal variables, the parameters passed to it, and arrays which it uses, either locally or as parameters.
The stateful scratchpad mode increases the size of the scratchpads from 64 elements to 256 elements each, but at the cost of making the condensed 16-bit memory-reference instructions available for either one or two data types at a time, although those data types can include any of the eight data types supported by the machine (even though the other instruction formats in that mode still only support a limited selection of types, for example, with opcode translation mode 000 in effect, not supporting the Long, Medium, and Quad types).
Note that only registers 0 to 3 can be the destination registers for a normal compact instruction in scratchpad mode; the instructions which use indirect or indirect post-indexed addressing always have register 0 as their destination register.
Mutable scratchpad mode is identical to stateful scratchpad mode, except that every memory reference instruction not using the scratchpad areas is treated as also including an implied SETPT or SETST instruction corresponding to the type of its operands.
If the two bits in the Program Status Block controlling the instruction type tracking mode are set to 00, indicating fixed-point priority mode, this operates as follows:
If the instruction acts on operands of a fixed-point type, the implied instruction is a SETPT instruction setting the primary type to that type, and resetting the bit indicating whether a secondary type is in use to indicate one is not in use, and if the instruction acts on operands of a floating-point type, the implied instruction is a SETST instruction setting the secondary type to that type, and setting the bit indicating whether a secondary type is in use to indicate that one is in use.
If the two bits in the Program Status Block controlling the instruction type tracking mode are set to 01, indicating floating-point priority mode, this operates as follows:
If the instruction acts on operands of a fixed-point type, the implied instruction is a SETST instruction setting the secondary type to that type, and setting the bit indicating whether a secondary type is in use to indicate that one is in use, and if the instruction acts on operands of a floating-point type, the implied instruction is a SETPT instruction setting the primary type to that type.
If the two bits in the Program Status Block controlling the instruction type tracking mode are set to 10, indicating passive fixed mode, this operates as follows:
If the instruction acts on operands of a fixed-point type, the implied instruction is a SETST instruction setting the secondary type to that type, and setting the bit indicating whether a secondary type is in use to indicate that one is in use, and if the instruction acts on operands of a floating-point type, it has no effect on either the primary or secondary type.
If the two bits in the Program Status Block controlling the instruction type tracking mode are set to 11, indicating dual floating mode, this operates as follows:
If the instruction acts on operands of a fixed-point type, it has no effect on either the primary or secondary type, and if the instruction acts on operands of a floating-point type, the implied instruction is a SETPT instruction setting the primary type to that type. Thus, the secondary type has to be set explicitly by a SETST instruction in this mode, and will not be changed by instruction execution.
This tracking mode is set by the SPSITTM (Set Primary/Secondary Instruction Type Tracking Mode) mode-independent instruction.
Note that the tracking of instruction types also takes place for instructions from other modes accessed by means of an INWM instruction. In addition, it also takes place for instructions executed while in another mode, if mutable scratchpad mode is the most recent of mutable scratchpad mode, stateful scratchpad mode and mixed operand mode in which the current instruction stream was operating prior to the execution of those instructions. Mixed operand mode uses the same bits in the Program Status Block that keep track of the primary and secondary instruction type for these modes for a different, but similar, purpose.
The six-bit opcodes of memory reference instructions in this mode are translated into seven-bit opcodes using the same eight possible schemes as used with extended operate mode:
Six-Bit Opcode Translate Field Value
000 001 010 011
000 0000 Byte 0000 Byte 0010 Halfword 0010 Halfword
001 0001 0001 0011 0011
010 0010 Halfword 0100 Integer 0100 Integer 0100 Integer
011 0011 0101 0101 0101
100 0100 Integer 0110 Long 0110 Long 0110 Long
101 0101 0111 0111 0111
110 1001 Floating 1001 Floating 1001 Floating 1010 Double
111 1010 Double 1010 Double 1010 Double 1011 Quad
Six-Bit Opcode Translate Field Value
100 101 110 111
000 0010 Halfword 0100 Integer 0000 Byte 0000 Byte
001 0011 0101 0010 Halfword 0001
010 0100 Integer 0110 Long 0100 Integer 0010 Halfword
011 0101 0111 0110 Long 0011
100 1000 Medium 1000 Medium 1000 Medium 0100 Integer
101 1001 Floating 1001 Floating 1001 Floating 0101
110 1010 Double 1010 Double 1010 Double 0110 Long
111 1011 Quad 1011 Quad 1011 Quad 0111
Note that in scratchpad mode, a register-register store instruction is meaningful, as such an instruction is required when it is desired to store values in registers 4 through 7.
In stateless scratchpad mode, sA (source address) indicates one of 64 elements, and in stateful scratchpad mode, one of 256 elements, of an array of values; for each of the operand types supported in scratchpad mode, there are three pointer registers, one for simple variables, used for a normal scratchpad instruction, one for pointers, used for an indirect mode instruction, and one for array pointers, used for an indirect post-indexed instruction.
The operand types are associated with the following numbers:
000 Byte 001 Halfword 010 Integer 011 Long 100 Medium 101 Floating 110 Double 111 Quad
and a full set of eight pointer registers of each of the three types is present. Although the long, medium, and quad ones are not used with stateless scratchpad instructions, they are available with stateful scratchpad instructions.
Setting the mode used with stateful scratchpad mode to a fixed-point data type causes all four bits of the opcode to be interpreted as they would be as the last four bits of the opcode of a standard memory reference instruction for that type. In the program status word, it sets the two bits representing the fixed type to the last two bits of the type designation shown above, and it clears the bit indicating that a secondary type is present.
Setting the mode to a floating-point data type causes opcodes of the form 1xxx to be interpreted as supplying the last three bits of the opcode of a standard memory reference instruction for that floating point type, and opcodes of the form 0xxx to be interpreted as the last four bits of the opcode of a standard memory reference instruction for the previously specified fixed-point type. In the program status word, it sets the two bits representing the floating type to the last two bits of the type designation for that type shown above, and it sets the bit indicating that a secondary type is present.
Thus, one can either be able to use only all the memory reference instructions for a single fixed-point type, both arithmetic and logical, or one can use the arithmetic memory reference instructions for both a fixed-point type and a floating-point type.
Thus, the possible four-bit opcodes in this mode represent the following instructions:
0000 SWPSP Swap Primary Scratchpad 0001 CPSP Compare Primary Scratchpad 0010 LPSP Load Primary Scratchpad 0011 STPSP Store Primary Scratchpad 0100 APSP Add Primary Scratchpad 0101 SPSP Subtract Primary Scratchpad 0110 MPSP Multiply Primary Scratchpad 0111 DPSP Divide Primary Scratchpad 1000 IPSP Insert Primary Scratchpad SWSSP Swap Secondary Scratchpad 1001 UCPSP Unsigned Compare Primary Scratchpad CSSP Compare Secondary Scratchpad 1010 ULPSP Unsigned Load Primary Scratchpad LSSP Load Secondary Scratchpad 1011 XPSP XOR Primary Scratchpad STSSP Store Secondary Scratchpad 1100 NPSP AND Primary Scratchpad ASSP Add Secondary Scratchpad 1101 OPSP OR Primary Scratchpad SSSP Subtract Secondary Scratchpad 1110 MEPSP Multiply Extensibly Primary Scratchpad MSSP Multiply Secondary Scratchpad 1111 DEPSP Divide Extensibly Primary Scratchpad DSSP Divide Secondary Scratchpad
and the data types which serve as the primary scratchpad type and the secondary scratchpad type are chosen by means of the SETPT and SETST instructions, described in the section on mode-independent instructions.
This mode is similar to stateful scratchpad mode, except that instead of having a primary type and a secondary type for instructions with four-bit opcodes, only one type is present. This type is stored in the same field of the Program Status Block as is used for the type used in the stack modes.
In this mode, the four-bit opcodes are defined to have the meanings:
0000 SWSP Swap Scratchpad 0001 CSP Compare Scratchpad 0010 LSP Load Scratchpad 0011 STSP Store Scratchpad 0100 ASP Add Scratchpad 0101 SSP Subtract Scratchpad 0110 MSP Multiply Scratchpad 0111 DSP Divide Scratchpad 1000 ISP Insert Scratchpad MEUSP Multiply Extensibly Unnormalized Scratchpad 1001 UCSP Unsigned Compare Scratchpad DEUSP Divide Extensibly Unnormalized Scratchpad 1010 ULSP Unsigned Load Scratchpad LUSP Load Unnormalized Scratchpad 1011 XSP XOR Scratchpad STUSP Store Unnormalized Scratchpad 1100 NSP AND Scratchpad AUSP Add Unnormalized Scratchpad 1101 OSP OR Scratchpad SUSP Subtract Unnormalized Scratchpad 1110 MESP Multiply Extensibly Scratchpad MUSP Multiply Unnormalized Scratchpad 1111 DESP Divide Extensibly Scratchpad DUSP Divide Unnormalized Scratchpad
thus, the unnormalized arithmetic instructions are included, so that both integer and floating-point types have sixteen basic opcodes associated with them.
The SETT instruction is the one used to select which type is used with four-bit opcodes in this mode.
This mode is similar to Plain Stateful Scratchpad Mode, except that standard memory-reference instructions automatically cause the type used for subsequent scratchpad instructions to change to the type used by those instructions.
The instruction formats available in this mode are shown below:
This instruction mode includes a 16-bit shift instruction and a 16-bit instruction which permits operations involving the first four arithmetic/index registers (or the first four floating-point registers) and any of the sixty-four supplementary registers. Opcode space for this is made available by limiting indexed memory-reference instructions to the use of only four destination registers.
This mode attempts to make efficient use of opcode space, and provide scratchpad operation as well, in another way. Base register zero is used to contain, in its least significant six bits, three bits indicating the primary base register and three bits indicating the alternate base register. In a memory-reference instruction, the address field is 15 bits long, and the first bit of the 16-bit halfword which contains it is either 0, indicating that the primary base register is used, or 1, indicating that the secondary base register is used. Either of the three-bit fields in base register zero may be zero; when that is the case, the corresponding value of the base register selection bit indicates absolute addressing.
The instruction formats available in this mode are shown below:
Only direct addressing is available for scratchpad instructions, and so only the eight scratchpad registers are used to point to the scratchpads for each type. Only registers 0 and 1 may serve as destination registers for these instructions. The opcode field is only five bits long, and with the default translation, as indicated by 000 in the six-bit opcode translation field of the Program Status Block, also used to indicate how five-bit opcodes are translated, the most basic types and operations remain available. The possible translations are shown below:
Six-Bit Opcode Translate Field Value
000 001 010 011
00 0100 Integer 0110 Long 0010 Halfword 0100 Integer
01 0101 0111 0011 0101
10 1001 Floating 1001 Floating 1001 Floating 1010 Double
11 1010 Double 1010 Double 1010 Double 1011 Quad
Six-Bit Opcode Translate Field Value
100 101 110 111
00 1000 Medium 0010 Halfword 0000 Byte
01 1001 Floating 0100 Integer 0001
10 1010 Double 1001 Floating 0100 Integer
11 1011 Quad 1010 Double 0101