This section describes two addressing modes which use different techniques to provide more in an instruction. Full Opcode Mode allows the use of eight-bit opcodes by limiting which registers can be used in some capacities in an indexed instruction. Comprehensive Mode also does this, but in addition uses six-bit opcodes; this makes room for the extended operate instructions and the short form of the shift instruction; as well, some unused opcode space in the range of the extended operate instructions is used for long vector instructions offering a subset of the capabilities of vector register mode.
In this mode, instructions have the form shown below:
All the memory-reference instructions, as well as register-to-register instructions, have an eight-bit opcode field which may contain any value, thus providing 256 possible opcodes instead of only 96, as provided by the usual seven-bit opcode field at the beginning of an instruction, as space is required for the operate instructions as well.
The indexed instructions can only use arithmetic/index registers 1, 2, and 3 as index registers. Both the indexed instructions and the indirect instructions can use only registers 0 and 1 of the appropriate type as their destination registers.
The eight-bit opcode field allows additional data types to be directly acted upon by standard memory-reference instructions, the opcodes of which now become:
0000xx SWB Swap Byte 0001xx CB Compare Byte 0002xx LB Load Byte 0003xx STB Store Byte 0004xx AB Add Byte 0005xx SB Subtract Byte 0010xx IB Insert Byte 0011xx UCB Unsigned Compare Byte 0012xx ULB Unsigned Load Byte 0013xx XB XOR Byte 0014xx NB AND Byte 0015xx OB OR Byte 0017xx STGB Store if Greater Byte 0020xx SWB Swap Halfword 0021xx CB Compare Halfword 0022xx LB Load Halfword 0023xx STB Store Halfword 0024xx AB Add Halfword 0025xx SB Subtract Halfword 0026xx MH Multiply Halfword 0027xx DH Divide Halfword 0030xx IB Insert Halfword 0031xx UCB Unsigned Compare Halfword 0032xx ULB Unsigned Load Halfword 0033xx XB XOR Halfword 0034xx NB AND Halfword 0035xx OB OR Halfword 0036xx MEH Multiply Extensibly Halfword 0037xx DEH Divide Extensibly Halfword 0040xx SW Swap 0041xx C Compare 0042xx L Load 0043xx ST Store 0044xx A Add 0045xx S Subtract 0046xx M Multiply 0047xx D Divide 0051xx UC Unsigned Compare 0053xx X XOR 0054xx N AND 0055xx O OR 0056xx ME Multiply Extensibly 0057xx DE Divide Extensibly 0060xx SWL Swap Long 0061xx CL Compare Long 0062xx LL Load Long 0063xx STL Store Long 0064xx AL Add Long 0065xx SL Subtract Long 0066xx ML Multiply Long 0067xx DL Divide Long 0071xx UCL Unsigned Compare Long 0073xx XL XOR Long 0074xx NL AND Long 0075xx OL OR Long 0076xx MEL Multiply Extensibly Long 0077xx DEL Divide Extensibly Long 0100xx SWM Swap Medium 0101xx CM Compare Medium 0102xx LM Load Medium 0103xx STM Store Medium 0104xx AM Add Medium 0105xx SM Subtract Medium 0106xx MM Multiply Medium 0107xx DM Divide Medium 0110xx MEUM Multiply Extensibly Unnormalized Medium 0111xx DEUM Divide Extensibly Unnormalized Medium 0112xx LUM Load Unnormalized Medium 0113xx STUM Store Unnormalized Medium 0114xx AUM Add Unnormalized Medium 0115xx SUM Subtract Unnormalized Medium 0116xx MUM Multiply Unnormalized Medium 0117xx DUM Divide Unnormalized Medium 0120xx SWF Swap Floating 0121xx CF Compare Floating 0122xx LF Load Floating 0123xx STF Store Floating 0124xx AF Add Floating 0125xx SF Subtract Floating 0126xx MF Multiply Floating 0127xx DF Divide Floating 0130xx MEU Multiply Extensibly Unnormalized 0131xx DEU Divide Extensibly Unnormalized 0132xx LU Load Unnormalized 0133xx STU Store Unnormalized 0134xx AU Add Unnormalized 0135xx SU Subtract Unnormalized 0136xx MU Multiply Unnormalized 0137xx DU Divide Unnormalized 0140xx SWD Swap Double 0141xx CD Compare Double 0142xx LD Load Double 0143xx STD Store Double 0144xx AD Add Double 0145xx SD Subtract Double 0146xx MD Multiply Double 0147xx DD Divide Double 0150xx MEUD Multiply Extensibly Unnormalized Double 0151xx DEUD Divide Extensibly Unnormalized Double 0152xx LUD Load Unnormalized Double 0153xx STUD Store Unnormalized Double 0154xx AUD Add Unnormalized Double 0155xx SUD Subtract Unnormalized Double 0156xx MUD Multiply Unnormalized Double 0157xx DUD Divide Unnormalized Double 0160xx SWQ Swap Quad 0161xx CQ Compare Quad 0162xx LQ Load Quad 0163xx STQ Store Quad 0164xx AQ Add Quad 0165xx SQ Subtract Quad 0166xx MQ Multiply Quad 0167xx DQ Divide Quad 0170xx MEUQ Multiply Extensibly Unnormalized Quad 0171xx DEUQ Divide Extensibly Unnormalized Quad 0172xx LUQ Load Unnormalized Quad 0173xx STUQ Store Unnormalized Quad 0174xx AUQ Add Unnormalized Quad 0175xx SUQ Subtract Unnormalized Quad 0176xx MUQ Multiply Unnormalized Quad 0177xx DUQ Divide Unnormalized Quad 0220xx SFSWL Simple Floating Swap Halfword 0221xx SFCL Simple Floating Compare Halfword 0222xx SFLL Simple Floating Load Halfword 0223xx SFSTL Simple Floating Store Halfword 0224xx SFAL Simple Floating Add Halfword 0225xx SFSL Simple Floating Subtract Halfword 0226xx SFML Simple Floating Multiply Halfword 0227xx SFDL Simple Floating Divide Halfword 0230xx SFMEUH Simple Floating Multiply Extensibly Unnormalized Halfword 0231xx SFDEUH Simple Floating Divide Extensibly Unnormalized Halfword 0232xx SFLUH Simple Floating Load Unnormalized Halfword 0233xx SFSTUH Simple Floating Store Unnormalized Halfword 0234xx SFAUH Simple Floating Add Unnormalized Halfword 0235xx SFSUH Simple Floating Subtract Unnormalized Halfword 0236xx SFMUH Simple Floating Multiply Unnormalized Halfword 0237xx SFDUH Simple Floating Divide Unnormalized Halfword 0240xx SFSW Simple Floating Swap 0241xx SFC Simple Floating Compare 0242xx SFL Simple Floating Load 0243xx SFST Simple Floating Store 0244xx SFA Simple Floating Add 0245xx SFS Simple Floating Subtract 0246xx SFM Simple Floating Multiply 0247xx SFD Simple Floating Divide 0250xx SFMEU Simple Floating Multiply Extensibly Unnormalized 0251xx SFDEU Simple Floating Divide Extensibly Unnormalized 0252xx SFLU Simple Floating Load Unnormalized 0253xx SFSTU Simple Floating Store Unnormalized 0254xx SFAU Simple Floating Add Unnormalized 0255xx SFSU Simple Floating Subtract Unnormalized 0256xx SFMU Simple Floating Multiply Unnormalized 0257xx SFDU Simple Floating Divide Unnormalized 0260xx SFSWL Simple Floating Swap Long 0261xx SFCL Simple Floating Compare Long 0262xx SFLL Simple Floating Load Long 0263xx SFSTL Simple Floating Store Long 0264xx SFAL Simple Floating Add Long 0265xx SFSL Simple Floating Subtract Long 0266xx SFML Simple Floating Multiply Long 0267xx SFDL Simple Floating Divide Long 0270xx SFMEUL Simple Floating Multiply Extensibly Unnormalized Long 0271xx SFDEUL Simple Floating Divide Extensibly Unnormalized Long 0272xx SFLUL Simple Floating Load Unnormalized Long 0273xx SFSTUL Simple Floating Store Unnormalized Long 0274xx SFAUL Simple Floating Add Unnormalized Long 0275xx SFSUL Simple Floating Subtract Unnormalized Long 0276xx SFMUL Simple Floating Multiply Unnormalized Long 0277xx SFDUL Simple Floating Divide Unnormalized Long 0301xx RPC Register Packed Compare 0302xx RPME Register Packed Multiply Extensibly 0303xx RPDE Register Packed Divide Extensibly 0304xx RPA Register Packed Add 0305xx RPS Register Packed Subtract 0306xx RPM Register Packed Multiply 0307xx RPD Register Packed Divide 0311xx RPCL Register Packed Compare Long 0312xx RPMEL Register Packed Multiply Extensibly Long 0313xx RPDEL Register Packed Divide Extensibly Long 0314xx RPAL Register Packed Add Long 0315xx RPSL Register Packed Subtract Long 0316xx RPML Register Packed Multiply Long 0317xx RPDL Register Packed Divide Long 0321xx RCDC Register Compressed Decimal Compare 0322xx RCDME Register Compressed Decimal Multiply Extensibly 0323xx RCDDE Register Compressed Decimal Divide Extensibly 0324xx RCDA Register Compressed Decimal Add 0325xx RCDS Register Compressed Decimal Subtract 0326xx RCDM Register Compressed Decimal Multiply 0327xx RCDD Register Compressed Decimal Divide 0331xx RCDCL Register Compressed Decimal Compare Long 0332xx RCDMEL Register Compressed Decimal Multiply Extensibly Long 0333xx RCDDEL Register Compressed Decimal Divide Extensibly Long 0334xx RCDAL Register Compressed Decimal Add Long 0335xx RCDSL Register Compressed Decimal Subtract Long 0336xx RCDML Register Compressed Decimal Multiply Long 0337xx RCDDL Register Compressed Decimal Divide Long 0340xx SWMDE Swap Medium Decimal Exponent 0341xx CMDE Compare Medium Decimal Exponent 0342xx LMDE Load Medium Decimal Exponent 0343xx STMDE Store Medium Decimal Exponent 0344xx AMDE Add Medium Decimal Exponent 0345xx SMDE Subtract Medium Decimal Exponent 0346xx MMDE Multiply Medium Decimal Exponent 0347xx DMDE Divide Medium Decimal Exponent 0352xx LUMDE Load Unnormalized Medium Decimal Exponent 0353xx STUMDE Store Unnormalized Medium Decimal Exponent 0354xx AUMDE Add Unnormalized Medium Decimal Exponent 0355xx SUMDE Subtract Unnormalized Medium Decimal Exponent 0356xx MUMDE Multiply Unnormalized Medium Decimal Exponent 0357xx DUMDE Divide Unnormalized Medium Decimal Exponent 0360xx SWDDE Swap Double Decimal Exponent 0361xx CDDE Compare Double Decimal Exponent 0362xx LDDE Load Double Decimal Exponent 0363xx STDDE Store Double Decimal Exponent 0364xx ADDE Add Double Decimal Exponent 0365xx SDDE Subtract Double Decimal Exponent 0366xx MDDE Multiply Double Decimal Exponent 0367xx DDDE Divide Double Decimal Exponent 0372xx LUDDE Load Unnormalized Double Decimal Exponent 0373xx STUDDE Store Unnormalized Double Decimal Exponent 0374xx AUDDE Add Unnormalized Double Decimal Exponent 0375xx SUDDE Subtract Unnormalized Double Decimal Exponent 0376xx MUDDE Multiply Unnormalized Double Decimal Exponent 0377xx DUDDE Divide Unnormalized Double Decimal Exponent
Unnormalized floating-point operation is described in a previous section, as are the other special data types used in the additional instructions made available here. Recall that the Simple Floating data type deals with pairs of integers, and thus only even-numbered registers can be used with the Simple Floating and Simple Floating Halfword types; for the Simple Floating Long data type, only arithmetic/index registers 0 and 4 can be used as register operands.
This mode includes, in addition to the operate instructions in the same format as in normal mode, the instruction formats shown here:
By combining the use of six-bit opcodes with the technique also used in simple compact mode and stack mode, which is a modification of the technique used in full opcode mode as shown above, to reduce the opcode space required by the indexed memory-reference instructions, it becomes possible to introduce some long vector instructions. These instructions treat the sixty-four supplementary registers as a vector accumulator, and in addition use the long vector registers, eight sets of sixty-four registers, and the long vector scratchpad, sixty-four sets of sixty-four registers. They do not attempt, unlike the case in vector register mode, to use the supplementary registers as index registers, or the scratchpad registers as additional base registers.
The long vector instructions use eight-bit full opcodes, and are situated in unused opcode space just after the bit field instructions. These instructions have a symmetric format, and four examples illustrating the mode bit values for the second operand are shown in the diagram. The first eight bits, as well as the last eight bits, of the third 16-bit halfword of the instruction, can refer to the supplementary registers, one of the eight vector registers, or to memory, as an operand, in addition to one of the sixty-four elements of the vector scratchpad, as well. Memory to memory long vector instructions do not have a starting and ending supplementary register, but instead have a 16-bit length field, and this format is distinguished by a bit in the first 16 bits of the instruction, as can be seen in the diagram. Although the bits in these instructions corresponding to the mode bits in the previous instruction format are also set so as to indicate memory operands, other operand types are not possible with these instructions. The use of the mask register field, and other aspects of long vector instructions, was discussed in the preceding section on vector register mode.
This opcode space also is used to make available longer full-opcode versions of the standard memory-reference instructions, whose addressing modes are indicated in a fashion analogous to that used for memory-reference instructions in normal mode.