In addition to describing the form of the standard operate instructions, as modified for this instruction mode (primarily due to the fact that the number of base registers has been increased to thirty-two from eight), this page also describes the extended operate instructions, which are available from within this mode.
The format of the operate instructions is significantly modified in this mode as well, and the format of the character, packed decimal, and related instructions are shown in this diagram:
and the form of the other operate instructions is shown here:
In this mode, the opcodes of the multiple register instructions are:
1520xx LM Load Multiple 1530xx STM Store Multiple 1521xx LMQ Load Multiple Quad 1531xx STMQ Store Multiple Quad 1522xx LMS Load Multiple Supplementary 1532xx STMS Store Multiple Supplementary 1524xx LMAR Load Multiple Aux Registers 1534xx STMAR Store Multiple Aux Registers
where the aux registers are the 32 base registers native to this mode.
Note that while the opcode field is six bits long, six-bit to seven-bit opcode translation does not apply to it, as it is not used to signify any normal memory-reference instruction.
An unused bit in these instructions, if set to 1, instead indicates the setup instructions for Parallel RISC processing. Since the long vector registers imply the presence of 64 pairs of arithmetic/logic units, one a 64-bit integer unit and one a floating-point unit, adding 64 simple instruction decoding and control units, each with their own 16-bit program counter and four status bits for carry, overflow, zero, and negative did not seem to involve adding too much to the hardware already present. These 64 processors each use 64 kilobytes of cache memory as their memory, and the setup instructions transfer information between main memory and that reserved section of cache. This feature is described in detail later, in a chapter of its own.
Also note that while there are additional forms of the shift instructions present, since the bits of the first word that are zero in a shift instruction are not used, the availability of the mode-independent instructions in this mode is not affected by this. Since the long vector integer ALUs must have the ability to perform shift operations in order to allow cache-internal parallel programming, it is only natural that there would also be actual shift instructions that involve them.
As well, only five of the eight possible modes of the Extensible Shift operations are shown. The second-to-last octal digit of the first 16 bits of the instruction indicates by its first bit whether the operation is a scalar or vector operation; the second bit indicates whether the source operand is one of eight registers or vector registers, if it is zero, or one of 64 elements of either the scratchpad or the vector scratchpad, if it is one, and the third bit indicates the same for the destination operand.
The extended operate instructions are also available in this mode, and their instructions are somewhat similar to those used in extended operate mode, but modified as necessary to reflect the fact that in this mode, as in vector register mode, there are thirty-two base registers used rather than eight, and to fit into the limited opcode space that remains available:
Due to the very limited amount of opcode space available, note that the decoding of the bit matrix register load and bit matrix register sum of products instructions is significantly changed from that in extended operate mode; here, opcodes which would otherwise indicate a bit matrix multiply instruction with the same source and destination registers are used.
The bit field and bit field string instructions follow the three-way and four-way vector operations within the opcode space continuing from the scratchpad memory reference and vector to vector scratchpad formats, while the bit-matrix multiply and population count instructions are located within an area of opcode space that could otherwise have been able to support an additional first-level addressing mode after the vector register constant mode. This area of opcode space is not fully independent; the related portion of opcode space that would contain associated second-level addressing modes is instead used by the floating-point two-way vector operations. The diagram below illustrates how these instructions share the available opcode space:
Recall that the first two bits of a seven-bit opcode, here moved to the two-bit op field following the five-bit op field in a standard memory-reference instruction, can only be 00, 01, or 10, and never 11. This makes available the space used by the two-way fixed-point instructions; the two-way floating-point instructions are in an analogous position, following the extended operate instructions.