This section describes Short Shift Mode, which uses the additional space derived from using six-bit opcodes for a short form of the shift instructions instead of for extended operate instructions, Condensed Mode, which uses this same additional space to allow two register-to-register operations to be placed in a single 16-bit word, and Vector Mode, in which six-bit opcodes are used, and, in addition, the registers that can be used as destination registers are limited in some instructions, in order to provide room for memory-to-memory vector operations.
In short shift mode, the memory-reference instructions have the same format as in extended operate mode. The instructions which begin with the bits 10, however, instead of being the extended operate instructions, are a modified form of the shift instructions which now occupy 16 bits rather than 32 bits. Thus, the memory-reference instructions and the new short shift instructions have the following form in this mode:
The opcodes of the shift instructions in this mode are:
100xxx SHLB Shift Left Byte 101xxx SHRB Shift Right Byte 103xxx ASRB Arithmetic Shift Right Byte 104xxx ROLB Rotate Left Byte 105xxx RORB Rotate Right Byte 106xxx RLCB Rotate Left through Carry Byte 107xxx RRCB Rotate Right through Carry Byte 110xxx SHLH Shift Left Halfword 111xxx SHRH Shift Right Halfword 113xxx ASRH Arithmetic Shift Right Halfword 114xxx ROLH Rotate Left Halfword 115xxx RORH Rotate Right Halfword 116xxx RLCH Rotate Left through Carry Halfword 117xxx RRCH Rotate Right through Carry Halfword 120xxx SHL Shift Left 121xxx SHR Shift Right 123xxx ASR Arithmetic Shift Right 124xxx ROL Rotate Left 125xxx ROR Rotate Right 126xxx RLC Rotate Left through Carry 127xxx RRC Rotate Right through Carry 130xxx SHLL Shift Left Long 131xxx SHRL Shift Right Long 133xxx ASRL Arithmetic Shift Right Long 134xxx ROLL Rotate Left Long 135xxx RORL Rotate Right Long 136xxx RLCL Rotate Left through Carry Long 137xxx RRCL Rotate Right through Carry Long
The scratchpad modes will attempt to replace memory-reference instructions, which occupy 32 bits, with instructions referring to one of 64 or 512 scratchpad locations which require only 16 bits.
The stack modes will provide an alternative to register-to-register instructions, by allowing three stack operations to fit into a single 16-bit word.
Condensed mode provides a different alternative to register-to-register instructions; a single 16-bit word can contain two instructions, each of which has register 0 as its destination, and one of the other registers as its source. The operand type used in these instructions is determined as in plain mutable scratchpad mode: it is the simple three-bit stack operand type, and it is set by any normal memory-reference instruction to the type referenced by that instruction.
The format of instructions in this mode is:
The data type used with the four-bit opcodes of these condensed instructions is selected by means of the SETT instruction, which is described in the section on mode-independent instructions. The possible operations that may be performed on each type are as follows:
0000 SWSP Swap Scratchpad 0001 CSP Compare Scratchpad 0010 LSP Load Scratchpad 0011 STSP Store Scratchpad 0100 ASP Add Scratchpad 0101 SSP Subtract Scratchpad 0110 MSP Multiply Scratchpad 0111 DSP Divide Scratchpad 1000 ISP Insert Scratchpad MEUSP Multiply Extensibly Unnormalized Scratchpad 1001 UCSP Unsigned Compare Scratchpad DEUSP Divide Extensibly Unnormalized Scratchpad 1010 ULSP Unsigned Load Scratchpad LUSP Load Unnormalized Scratchpad 1011 XSP XOR Scratchpad STUSP Store Unnormalized Scratchpad 1100 NSP AND Scratchpad AUSP Add Unnormalized Scratchpad 1101 OSP OR Scratchpad SUSP Subtract Unnormalized Scratchpad 1110 MESP Multiply Extensibly Scratchpad MUSP Multiply Unnormalized Scratchpad 1111 DESP Divide Extensibly Scratchpad DUSP Divide Unnormalized Scratchpad
the selected type being called the scratchpad type, because type selection is most extensively used with the scratchpad instructions, to be described in a later section. This mode follows the pattern used in the plain scratchpad modes.
In vector mode, the memory reference instructions again have the same form as in extended operate mode, making room for two additional addressing modes for each memory reference instruction:
The vector instructions have three arguments, a source, an operand, and a destination. Thus, in a subtract instruction, the operand is subtracted from the source, and the result is placed in the destination; in a divide instruction, the source is divided by the operand, and the result is placed in the destination. All three arguments are arrays of consecutive elements of the appropriate type, and the number of elements, from 1 to 64, operated on by the instruction, is indicated by the value in the length field after it is increased by one; that is, a 0 in the length field indicates a vector of length 1, and a 63 in the length field indicates a vector of length 64.
Note that only arithmetic/index registers 1, 2, and 3 may be used as index registers with the operand argument of these instructions. This restriction allows these instructions to fit in the opcode space available without splitting any fields between halfwords.
Note that these vector instructions do not involve the short vector registers. Since they are memory to memory instructions, and the maximum length of a vector is quite large, they are essentially independent of the width of the bus or the size of the internal arithmetic unit in a particular implementation of this architecture.
The vector instructions involving the short vector registers, on the other hand, do make specific hardware demands; but instructions of that type are also useful in other applications.
In a constant instruction, there are two arguments in memory, and the operand is the same for every value in the vector, and is taken from a register. Note that this is the format that should be used for operations such as load and store where the operand is ignored.
Note also that for the multiply and divide extensibly instructions, not all the arguments to the instruction have the same length. The insert and unsigned load instructions are not available in vector instructions, and both arguments to the load instruction, which is to be used in preference to the store instruction, are treated as having the same length.
As the compare instruction is not usable with vectors, its opcode is used instead for another useful function, multiply and accumulate. If the default mapping of six-bit opcodes to seven-bit opcodes is in effect, the instructions this creates are:
1x21xx MAH Multiply and Accumulate Halfword 1x41xx MA Multiply and Accumulate 1x61xx MAF Multiply and Accumulate Floating 1x71xx MAD Multiply and Accumulate Double
The product of the source and operand arguments is added to the current contents of the destination argument.
By making the two compromises of restricting the address displacement field to 15 bits instead of 16 bits, and of restricting the destination of indexed instructions to register zero, it becomes possible to have enough remaining opcode space to have an eight-bit opcode field, to have 16-bit shift instructions, and to have the normal form of the operate instructions (as opposed to the form used with advanced compound mode and related modes which adds a 16-bit prefix to the operate instructions).
The opcodes of the memory reference instructions become:
0000xx SWB Swap Byte 0002xx CB Compare Byte 0004xx LB Load Byte 0006xx STB Store Byte 0010xx AB Add Byte 0012xx SB Subtract Byte 0020xx IB Insert Byte 0022xx UCB Unsigned Compare Byte 0024xx ULB Unsigned Load Byte 0026xx XB XOR Byte 0030xx NB AND Byte 0032xx OB OR Byte 0036xx STGB Store if Greater Byte 0040xx SWB Swap Halfword 0042xx CB Compare Halfword 0044xx LB Load Halfword 0046xx STB Store Halfword 0050xx AB Add Halfword 0052xx SB Subtract Halfword 0054xx MH Multiply Halfword 0056xx DH Divide Halfword 0060xx IB Insert Halfword 0062xx UCB Unsigned Compare Halfword 0064xx ULB Unsigned Load Halfword 0066xx XB XOR Halfword 0070xx NB AND Halfword 0072xx OB OR Halfword 0074xx MEH Multiply Extensibly Halfword 0076xx DEH Divide Extensibly Halfword 0100xx SW Swap 0102xx C Compare 0104xx L Load 0106xx ST Store 0110xx A Add 0112xx S Subtract 0114xx M Multiply 0116xx D Divide 0122xx UC Unsigned Compare 0126xx X XOR 0130xx N AND 0132xx O OR 0134xx ME Multiply Extensibly 0136xx DE Divide Extensibly 0140xx SWL Swap Long 0142xx CL Compare Long 0144xx LL Load Long 0146xx STL Store Long 0150xx AL Add Long 0152xx SL Subtract Long 0154xx ML Multiply Long 0156xx DL Divide Long 0162xx UCL Unsigned Compare Long 0166xx XL XOR Long 0170xx NL AND Long 0172xx OL OR Long 0174xx MEL Multiply Extensibly Long 0176xx DEL Divide Extensibly Long 0200xx SWM Swap Medium 0202xx CM Compare Medium 0204xx LM Load Medium 0206xx STM Store Medium 0210xx AM Add Medium 0212xx SM Subtract Medium 0214xx MM Multiply Medium 0216xx DM Divide Medium 0220xx MEUM Multiply Extensibly Unnormalized Medium 0222xx DEUM Divide Extensibly Unnormalized Medium 0224xx LUM Load Unnormalized Medium 0226xx STUM Store Unnormalized Medium 0230xx AUM Add Unnormalized Medium 0232xx SUM Subtract Unnormalized Medium 0234xx MUM Multiply Unnormalized Medium 0236xx DUM Divide Unnormalized Medium 0240xx SWF Swap Floating 0242xx CF Compare Floating 0244xx LF Load Floating 0246xx STF Store Floating 0250xx AF Add Floating 0252xx SF Subtract Floating 0254xx MF Multiply Floating 0256xx DF Divide Floating 0260xx MEU Multiply Extensibly Unnormalized 0262xx DEU Divide Extensibly Unnormalized 0264xx LU Load Unnormalized 0266xx STU Store Unnormalized 0270xx AU Add Unnormalized 0272xx SU Subtract Unnormalized 0274xx MU Multiply Unnormalized 0276xx DU Divide Unnormalized 0300xx SWD Swap Double 0302xx CD Compare Double 0304xx LD Load Double 0306xx STD Store Double 0310xx AD Add Double 0312xx SD Subtract Double 0314xx MD Multiply Double 0316xx DD Divide Double 0320xx MEUD Multiply Extensibly Unnormalized Double 0322xx DEUD Divide Extensibly Unnormalized Double 0324xx LUD Load Unnormalized Double 0326xx STUD Store Unnormalized Double 0330xx AUD Add Unnormalized Double 0332xx SUD Subtract Unnormalized Double 0334xx MUD Multiply Unnormalized Double 0336xx DUD Divide Unnormalized Double 0340xx SWQ Swap Quad 0342xx CQ Compare Quad 0344xx LQ Load Quad 0346xx STQ Store Quad 0350xx AQ Add Quad 0352xx SQ Subtract Quad 0354xx MQ Multiply Quad 0356xx DQ Divide Quad 0360xx MEUQ Multiply Extensibly Unnormalized Quad 0362xx DEUQ Divide Extensibly Unnormalized Quad 0364xx LUQ Load Unnormalized Quad 0366xx STUQ Store Unnormalized Quad 0370xx AUQ Add Unnormalized Quad 0372xx SUQ Subtract Unnormalized Quad 0374xx MUQ Multiply Unnormalized Quad 0376xx DUQ Divide Unnormalized Quad 0440xx SFSWL Simple Floating Swap Halfword 0442xx SFCL Simple Floating Compare Halfword 0444xx SFLL Simple Floating Load Halfword 0446xx SFSTL Simple Floating Store Halfword 0450xx SFAL Simple Floating Add Halfword 0452xx SFSL Simple Floating Subtract Halfword 0454xx SFML Simple Floating Multiply Halfword 0456xx SFDL Simple Floating Divide Halfword 0460xx SFMEUH Simple Floating Multiply Extensibly Unnormalized Halfword 0462xx SFDEUH Simple Floating Divide Extensibly Unnormalized Halfword 0464xx SFLUH Simple Floating Load Unnormalized Halfword 0466xx SFSTUH Simple Floating Store Unnormalized Halfword 0470xx SFAUH Simple Floating Add Unnormalized Halfword 0472xx SFSUH Simple Floating Subtract Unnormalized Halfword 0474xx SFMUH Simple Floating Multiply Unnormalized Halfword 0476xx SFDUH Simple Floating Divide Unnormalized Halfword 0500xx SFSW Simple Floating Swap 0502xx SFC Simple Floating Compare 0504xx SFL Simple Floating Load 0506xx SFST Simple Floating Store 0510xx SFA Simple Floating Add 0512xx SFS Simple Floating Subtract 0514xx SFM Simple Floating Multiply 0516xx SFD Simple Floating Divide 0520xx SFMEU Simple Floating Multiply Extensibly Unnormalized 0522xx SFDEU Simple Floating Divide Extensibly Unnormalized 0524xx SFLU Simple Floating Load Unnormalized 0526xx SFSTU Simple Floating Store Unnormalized 0530xx SFAU Simple Floating Add Unnormalized 0532xx SFSU Simple Floating Subtract Unnormalized 0534xx SFMU Simple Floating Multiply Unnormalized 0536xx SFDU Simple Floating Divide Unnormalized 0540xx SFSWL Simple Floating Swap Long 0542xx SFCL Simple Floating Compare Long 0544xx SFLL Simple Floating Load Long 0546xx SFSTL Simple Floating Store Long 0550xx SFAL Simple Floating Add Long 0552xx SFSL Simple Floating Subtract Long 0554xx SFML Simple Floating Multiply Long 0556xx SFDL Simple Floating Divide Long 0560xx SFMEUL Simple Floating Multiply Extensibly Unnormalized Long 0562xx SFDEUL Simple Floating Divide Extensibly Unnormalized Long 0564xx SFLUL Simple Floating Load Unnormalized Long 0566xx SFSTUL Simple Floating Store Unnormalized Long 0570xx SFAUL Simple Floating Add Unnormalized Long 0572xx SFSUL Simple Floating Subtract Unnormalized Long 0574xx SFMUL Simple Floating Multiply Unnormalized Long 0576xx SFDUL Simple Floating Divide Unnormalized Long 0602xx RPC Register Packed Compare 0604xx RPME Register Packed Multiply Extensibly 0606xx RPDE Register Packed Divide Extensibly 0610xx RPA Register Packed Add 0612xx RPS Register Packed Subtract 0614xx RPM Register Packed Multiply 0616xx RPD Register Packed Divide 0622xx RPCL Register Packed Compare Long 0624xx RPMEL Register Packed Multiply Extensibly Long 0626xx RPDEL Register Packed Divide Extensibly Long 0630xx RPAL Register Packed Add Long 0632xx RPSL Register Packed Subtract Long 0634xx RPML Register Packed Multiply Long 0636xx RPDL Register Packed Divide Long 0642xx RCDC Register Compressed Decimal Compare 0644xx RCDME Register Compressed Decimal Multiply Extensibly 0646xx RCDDE Register Compressed Decimal Divide Extensibly 0650xx RCDA Register Compressed Decimal Add 0652xx RCDS Register Compressed Decimal Subtract 0654xx RCDM Register Compressed Decimal Multiply 0656xx RCDD Register Compressed Decimal Divide 0662xx RCDCL Register Compressed Decimal Compare Long 0664xx RCDMEL Register Compressed Decimal Multiply Extensibly Long 0666xx RCDDEL Register Compressed Decimal Divide Extensibly Long 0670xx RCDAL Register Compressed Decimal Add Long 0672xx RCDSL Register Compressed Decimal Subtract Long 0674xx RCDML Register Compressed Decimal Multiply Long 0676xx RCDDL Register Compressed Decimal Divide Long 0700xx SWMDE Swap Medium Decimal Exponent 0702xx CMDE Compare Medium Decimal Exponent 0704xx LMDE Load Medium Decimal Exponent 0706xx STMDE Store Medium Decimal Exponent 0710xx AMDE Add Medium Decimal Exponent 0712xx SMDE Subtract Medium Decimal Exponent 0714xx MMDE Multiply Medium Decimal Exponent 0716xx DMDE Divide Medium Decimal Exponent 0724xx LUMDE Load Unnormalized Medium Decimal Exponent 0726xx STUMDE Store Unnormalized Medium Decimal Exponent 0730xx AUMDE Add Unnormalized Medium Decimal Exponent 0732xx SUMDE Subtract Unnormalized Medium Decimal Exponent 0734xx MUMDE Multiply Unnormalized Medium Decimal Exponent 0736xx DUMDE Divide Unnormalized Medium Decimal Exponent 0740xx SWDDE Swap Double Decimal Exponent 0742xx CDDE Compare Double Decimal Exponent 0744xx LDDE Load Double Decimal Exponent 0746xx STDDE Store Double Decimal Exponent 0750xx ADDE Add Double Decimal Exponent 0752xx SDDE Subtract Double Decimal Exponent 0754xx MDDE Multiply Double Decimal Exponent 0756xx DDDE Divide Double Decimal Exponent 0764xx LUDDE Load Unnormalized Double Decimal Exponent 0766xx STUDDE Store Unnormalized Double Decimal Exponent 0770xx AUDDE Add Unnormalized Double Decimal Exponent 0772xx SUDDE Subtract Unnormalized Double Decimal Exponent 0774xx MUDDE Multiply Unnormalized Double Decimal Exponent 0776xx DUDDE Divide Unnormalized Double Decimal Exponent
Note that it is possible, with any of these modes, for a register-to-register instruction with opcode 0 and source and destination registers 0 to be the prefix for an extended operate instruction, and a register-to-register instruction with both source and destination registers being the same and being 4, 5, 6, or 7 to be the prefix, including the opcode, for a long vector instruction, just as is the case with normal mode.