The mode of operation described in this section makes room for extra categories of instructions by using six-bit opcodes for standard memory-reference instructions. This can be achieved by using only the more common data types, using only 8, 16, and 32-bit fixed-point operands, and only 32 and 64-bit floating-point operands, but it is possible to select which set of data types is used.
In extended operate mode, the memory reference instructions have the following format:
and the special operation instructions have the same format as in the normal mode.
Initially, the seven-bit opcodes used when the computer is in normal mode were described. For extended operate mode, only six-bit opcode fields are shown. What are the operations to which the possible values in those fields correspond?
By default, the rule is that the opcodes beginning with 00, 01, and 10 are translated to seven-bit opcodes beginning with 000, 001, and 010, for access to the byte, halfword, and integer types, and opcodes beginning with 110 and 111 are translated to seven-bit opcodes beginning with 1001 and 1010 for access to the floating and double types. These are the most common operand types. But an alternate scheme of translation from six-bit opcodes to seven-bit opcodes may be selected from several predefined ones in order to obtain the one best suited to the requirements of a particular problem being solved by computer.
Six-bit opcodes are also used in several other modes of operation: among them are vector mode, stateful scratchpad mode, mutable scratchpad mode, and (for one instruction format only) full opcode mode.
The possible translations available for the first three bits of a six-bit opcode to the first four bits of a seven-bit opcode, based on the setting of the three bits in the six-bit opcode translate field of the Program Status Block, are as follows:
Six-Bit Opcode Translate Field Value
000 001 010 011
000 0000 Byte 0000 Byte 0010 Halfword 0010 Halfword
001 0001 0001 0011 0011
010 0010 Halfword 0100 Integer 0100 Integer 0100 Integer
011 0011 0101 0101 0101
100 0100 Integer 0110 Long 0110 Long 0110 Long
101 0101 0111 0111 0111
110 1001 Floating 1001 Floating 1001 Floating 1010 Double
111 1010 Double 1010 Double 1010 Double 1011 Quad
Six-Bit Opcode Translate Field Value
100 101 110 111
000 0010 Halfword 0100 Integer 0000 Byte 0000 Byte
001 0011 0101 0010 Halfword 0001
010 0100 Integer 0110 Long 0100 Integer 0010 Halfword
011 0101 0111 0110 Long 0011
100 1000 Medium 1000 Medium 1000 Medium 0100 Integer
101 1001 Floating 1001 Floating 1001 Floating 0101
110 1010 Double 1010 Double 1010 Double 0110 Long
111 1011 Quad 1011 Quad 1011 Quad 0111
The characteristics of these translation formats are:
These translation formats are chosen by means of the SETOTM instruction, described in the section on mode-independent instructions.
This mode provides for bit field operations, whose instructions have the following format:
and the opcodes
1001xx CBF Compare Bit Field 1002xx MBF Move Bit Field 1004xx ABF Add Bit Field 1005xx SBF Subtract Bit Field 1010xx NBF AND Bit Field 1011xx OBF OR Bit Field 1012xx XBF XOR Bit Field 1013xx SWBF Swap Bit Field
The six-bit length field of the instruction indicates the width of the field operated on in bits, minus one. The address field in the instruction and the index register contents, if indexing is used, are in units of bits, but the base register contents are still a byte address.
The IBM 7030 computer, also known as the STRETCH, and the Univac III were computers that operated on bit fields of arbitrary length with bit addressing.
In addition, another form of bit field instruction is provided, allowing operations similar to the string operations to be performed on bit fields:
Here, the size of the bit fields is given by the dSize and sSize fields, and the length field gives the number of bit fields acted upon. The C bit indicates that the value in the arithmetic/index register cR is used (or that register and the register following it if sSize is greater than 32) to perform the following operation on the bit field values read from the source parameter: the bits in the positions of the input bit field corresponding to the 1 bits in the condensing register are placed in order in the least significant bit positions of the destination bit field.
The opcode used in this format is:
1002xx MCBFS Move and Condense Bit Field String
This instruction is useful for translating between strings of bit fields and strings of bytes or other normally-aligned values which can then be efficiently operated on by other instructions.
Except for the fact that the condensed bits are placed in the least significant (rather than the most significant) portion of the result bit field, the condense operation which is repeatedly performed in this instruction is the same operation as is performed by the Pack instruction of the BESM-6 computer.
In normal operation, the bits of a byte are numbered from 0 to 7 from left to right. When the computer is operating in little-endian mode, with the bit indicating that the leftmost or most significant part of a quantity is in the portion with a higher address, the bits of a byte are numbered from 7 to 0 from left to right.
This permits bit addressing for these instructions to function in a consistent manner in both modes, as shown in the diagram below:
This diagram illustrates how another operation available in this mode functions:
This instruction, the SEBI (Separate Bits) instruction, with the opcode 11xxxn, operates on arithmetic/index registers n and n+1, performing up to fifteen operations in sequence on the contents of those two registers, as indicated by the last nine bits of the instruction.
The instruction with opcode 11737n of this type causes arithmetic/index register n+1 to contain a count of the number of 1 bits originally contained in both registers.
The instruction with opcode 11634n of this type causes the eight bytes of registers n and n+1 to each contain an 0 or a 1 depending on whether the corresponding bit of the last byte of register n+1 was initially an 0 or a 1.
The instruction with opcode 11234n of this type performs a matrix transpose on the 64 bits of those two registers, if they are thought of as being an 8 by 8 matrix of bits. Combining the 11634n and 11234n instructions with shift instructions permits the efficient manipulation of individual bits in a computer word.
Because the usefulness of the addition operation would be limited by unwanted carries if it is not accompanied by the preceding clear half operation, if the bit for the clear half operation is not set, the bit indicating the addition operation may be used to indicate a different operation instead. The bit shown as a constant zero in this mode, if changed to a 1, may indicate an instruction in which the bit interchanges shown occur in reverse and in reverse order, to form the COBI or Combine Bits instruction, but if so, that remains to be defined.
Another group of instructions available in this mode have the form:
The instructions illustrated in the first line of the diagram have the opcodes:
12x1xx BMM16 Bit Matrix Multiply 16 12x2xx BMM32 Bit Matrix Multiply 32 12x3xx BMM64 Bit Matrix Multiply 64
Those illustrated in the second line of the diagram have the opcodes:
12x400 00x1xx BMSP16 Bit-Matrix Sum of Products 16 12x400 00x2xx BMSP32 Bit-Matrix Sum of Products 32 12x400 00x3xx BMSP64 Bit-Matrix Sum of Products 64
and those illustrated in the third line of the diagram have the opcodes:
12x5xx LBMM16 Load Bit-Matrix-Multiply 16 12x6xx LBMM32 Load Bit-Matrix-Multiply 32 12x7xx LBMM64 Load Bit-Matrix-Multiply 64
The mR field in the instruction indicates one 256-bit short vector register for the BMM16 instruction. Originally, a group of four 256-bit short vector registers, with the values 0, 4, 8, and 12 indicating the first register of that group were the only ones allowed, for the BMM32 instruction, and that field was not used, and had necessarily been zero, in the BMM64 instruction.
However, as noted in the initial section of this page, implementations of this architecture may provide for register renaming to allow multiple threads to execute concurrently without context switching. Thus, it seemed reasonable to consider that a process might get more than its share of register space.
Even without taking such an extraordinary step, there is additional register space in the normal complement of registers that is only used in another mode, register scratchpad mode: thus, under normal circumstances, some additional values of the mR field in the BMM32 and BMM64 instructions are defined to make use of the supplementary floating-point registers. The table below shows how the mR field is interpreted normally, and when 4, 8, or 16 explicit bit-matrix-multiply register banks, each treated as containing 16 registers having the same size as a short vector register, have been allocated to a process:
no allocation 4 allocated 8/16 allocated 8 allocated 16 allocated
BMM16 BMM32 BMM64 BMM16 BMM32 BMM64 BMM16 BMM32 BMM64 BMM64
0 SV 0 SV 0-3 SV 0-15 BM 0 BM 0-3 BM 0-15 BM 64 BM 0-3 BM 0-15 BM 0-15
1 SV 1 BM 1 BM 4-7 BM 65 BM 4-7 BM 16-31
2 SV 2 SF 0-7 BM 2 BM 8-11 SV 0-15 BM 66 BM 8-11 BM 16-31 BM 32-47
3 SV 3 SF 8-15 BM 3 BM 12-15 BM 67 BM 12-15 SV 0-15 BM 48-63
4 SV 4 SV 4-7 BM 4 BM 16-19 BM 16-31 BM 68 BM 16-19 BM 32-47 BM 64-79
5 SV 5 BM 5 BM 20-23 BM 69 BM 20-23 BM 80-95
6 SV 6 SF 16-23 BM 6 BM 24-27 BM 70 BM 24-27 BM 48-63 BM 96-111
7 SV 7 SF 24-31 BM 7 BM 28-31 BM 71 BM 28-31 BM 112-127
8 SV 8 SV 8-11 SF 0-31 BM 8 BM 32-35 BM 32-47 BM 72 BM 32-35 BM 64-79 BM 128-143
9 SV 9 BM 9 BM 36-39 BM 73 BM 36-39 BM 144-159
10 SV 10 SF 32-39 BM 10 BM 40-43 SF 0-31 BM 74 BM 40-43 BM 80-95 BM 160-175
11 SV 11 SF 40-47 BM 11 BM 44-47 BM 75 BM 44-47 SF 0-31 BM 176-191
12 SV 12 SV 12-15 SF 32-63 BM 12 BM 48-51 BM 48-63 BM 76 BM 48-51 BM 96-111 BM 192-207
13 SV 13 BM 13 BM 52-55 BM 77 BM 52-55 BM 208-223
14 SV 14 SF 48-55 BM 14 BM 56-59 SF 32-63 BM 78 BM 56-59 BM 112-127 BM 224-239
15 SV 15 SF 56-63 BM 15 BM 60-63 BM 79 BM 60-63 SF 32-63 BM 240-255
These instructions perform a bit matrix multiply on values in the accumulator/index registers using the bits in the short vector register area to define the matrix. For the BMM16 instruction, the operands indicated by dR and sR are the least significant 16 bits of the registers they indicate; for the BMM32 instruction, they are the entire registers, and for the BMM64 instructions, they are pairs of registers, and the dR and sR fields, which indicate the first register of the pair, may only have the values 0, 2, 4, and 6. (This is not changed by the allocation of bit matrix multiply registers, of course.)
The logical operation performed to derive the output from the input, therefore, is that the source is ANDed to successive groups of 16, 32, or 64 bits in the bit-matrix-multiply register, and then all the bits in the 16, 32, or 64-bit long result are XORed together to form one bit in the final result.
These instructions allow the rapid application of matrix-based error-correcting codes, such as the Golay code, to data, and they also simplify some format conversion tasks.
The second line of the diagram above shows the format of an instruction which specifies two bit-matrix-multiply registers for another logical operation. Here, an intermediate result is formed by taking groups of bits from the input, selecting them by performing an OR with the inverse of the contents of the first bit-matrix multiply register, and then performing an AND over all the bits of the result to form one bit in the intermediate result. Then, bits from the intermediate result are selected by performing an AND with groups of bits from the second bit-matrix multiply, but this time a bit in the final result is formed by a normal inclusive OR over the bits of the result of the AND.
The bit matrix multiply registers allocated to a process, when the default six-bit opcode translation scheme is chosen, can be loaded by the instructions shown in the third line of the diagram above, and in which the sX and sB fields operate in the same manner as in standard memory-reference instructions.
The mR field in this instruction indicates the destination bit matrix multiply register in the same manner as the mR field in the BMM16, BMM32, or BMM64 instruction respectively, and so this instruction may, depending on the number of explicit bit matrix multiply registers allocated, load data into the short vector registers or the supplementary floating-point registers.
Note that it is possible with this mode, for a register-to-register instruction with both source and destination registers being the same and being 4, 5, 6, or 7 to be the prefix, including the opcode, for a long vector instruction, just as is the case with normal mode.