The computer has two hundred and fifty-six possible codes indicating the set of instruction formats, or addressing modes, in use, or the instruction mode of the computer.
The first bit of the eight-bit field used to indicate the instruction mode indicates if a direct cache mode is used; in a direct cache mode, half the possible codes for base registers are instead used to supply additional address bits for an address within high-speed cache memory, used instead as a high-speed conventional memory under program control.
Each group of 128 instruction modes is further divided into two major parts, but these are not of equal size; 96 ordinary instruction modes, with instructions that are built from 16-bit parts, and observe 16-bit alignment, and 32 variant alignment modes which may be aligned on 32-bit boundaries, 8-bit boundaries, or possibly boundaries of areas of other sizes.
At this time, sixteen of the codes in the first group of ninety-six have a defined meaning, and five of the thirty-two possible codes for variant alignment modes are defined.
The mode-independent instructions may be no longer available from within a variant alignment mode, or at least are modified in form, and explicit indication of parallelism is also either not available or modified in form (although it is also true of the conventional stack modes that explicit indication of parallelism is not available for them, since for those modes, it would not be useful, as successive instructions are almost always logically dependent).
The chart below shows the codes for the sixty-five available instruction modes with 16-bit alignment and their names, and then the codes for the instruction modes with variant alignment followed by, in four major columns (the third being divided into four columns in its own right),
16-bit alignment: 0 000 0000: normal mode -- 65,536 SV SU LV N 0 000 0001: aligned operand mode -- 65,536 SV SU LV N 0 000 1000: extended operate mode -- 65,536/8,192 SV * N 0 000 1011: aligned condensed mode 32,768 65.536 SV SU LV N 0 001 1000: symmetric address mode -- 65,536 SV N 0 001 1100: symmetric vector register mode 65,536* 65,536 * SV SU LV N* 0 010 0000: stateless scratchpad mode 64 65,536 SC SV N 0 010 0001: register scratchpad mode -- 65,536 SV SU N 0 010 0100: double base mode 256 32,768 S SV N 0 010 0101: flexible register mode -- 32,768/4,096 SV N 0 010 0111: simple compact mode -- 65,536 S SV SU N 0 010 1000: stateful scratchpad mode 512 65,536 SC SV N 0 010 1010: mutable scratchpad mode 512 65,536 SC SV N 0 010 1100: plain stateful scratchpad mode 512 65,536 SC SV N 0 010 1110: plain mutable scratchpad mode 512 65,536 SC SV N 0 011 0000: vector register mode 65,536* 65,536 * SV SU LV N* Variant alignment: (32-bit) 0 110 0000: aligned instruction mode 64 32,768 SC A 0 110 0110: general register mode -- 16,777,216* SV SU LV G (8-bit) 0 111 1000: three-address RISC mode -- 32,768 **** 0 111 1100: flexible CISC mode 65,536* 65,536 * SU 0 111 1101: stack machine mode -- 65,536
Because the size of a displacement used in conjunction with the specification of a base register differs from one mode to another, when values are placed in the base registers for use, a decision is being made which may potentially limit the usefulness of some modes.
In particular, a program written to make use of another mode might find, if attempting to switch into short page mode for some instructions, that additional base registers would need to be allocated in order to make use of a specific address. Switching from short page mode to one of the other modes to make use of specific instructions does not encounter a similar limitation, since now the switch is being made to a mode with larger addresses.
In vector register mode, the number in the first column is indicating the number of bytes pointed to: the scratchpad registers are used as additional base registers, and the supplementary registers are used as a scratchpad that consists of registers, rather than one pointed to by registers.
In the case of stack mode, the scratchpad registers are used to point to single elements within an area of memory that is of arbitrary size, only determined by the amount of memory allocated for each of the eight stacks.
For short page compact mode, the scratchpad registers point to areas of memory 512 bytes in size; this is indicated by note A in this column; for the extended short page modes, the array scratchpad registers point to areas of memory 258,435,456 bytes in size (switching to this from a 4,096 byte page pointed to by the regular base registers being done within the instruction, instead of by the 32/28-bit addressing bit in the Program Status Block), and this is indicated by note B in this column. In universal mode, the scratchpad registers point to areas of memory 258,435,456 bytes in size, the pointer scratchpad registers point to areas of memory 65,536 halfwords in size, and the array scratchpad registers point to areas 4,096 words or 4,096 doublewords in size, indicated by note C in this column.
In the case of extended operate mode, the dual entry for the area of memory referenced by a given base register reflects the fact that in the bit field instructions, the address field of the instruction is taken to be a bit address, and thus covers a smaller expanse of memory.
The basic registers used in all modes except general register mode are the eight arithmetic/index registers, the eight base registers, and the eight floating-point registers. In general register mode, the supplementary registers are used for the functions of these registers, and thus the figure given for the size of the area to which a base register points, marked with an asterisk for this mode, indicates the size of the area to which a supplementary register points when used as a base register.
SC stands for the scratchpad registers. These are three additional banks of eight registers which are similar to the base registers. They are also used to point to the beginning of an area in memory, but that area is usually smaller than that which a base register points to.
In stateless scratchpad mode, stateful scratchpad mode, mutable scratchpad mode, and short page mode, these registers are used to make instructions possible that reference memory but which are only 16 bits long, by pointing to areas of memory within which items can be accessed with short addresses.
In double base mode, only the first set of eight scratchpad registers are used; this is indicated by putting S instead of SC in this column.
The three banks of scratchpad registers are also used in register scratchpad mode and symmetric vector register mode, but in these modes they are merely used as additional base registers, increasing the number of base registers from 8 to 32. Thus, an asterisk is placed in this column for those modes. The scratchpad referred to in the name of this mode consists of the two groups of 64 supplementary registers.
The supplementary memory reference instructions can access the scratchpad registers in all modes, but no entries are placed in this column simply to reflect that fact.
In aligned stack mode, the eight scratchpad registers are used as stack pointers, but the scratchpad pointer registers and the array scratchpad registers are not directly used, hence an entry of two asterisks appears at that point in the table.
SV stands for the short vector registers. These are a bank of sixteen registers, each 256 bits in length, which can be treated as vectors of 32 bytes, 16 halfwords, 8 integers, or 4 long integers, as well as 8 floating-point numbers, 4 double-precision floating-point numbers, or 2 quad-precision floating-point numbers. They are used by instructions in normal mode, and in those modes where the available memory-reference addressing modes did not make it necessary to cut in half the opcode space available for the other instructions. Thus, they are used in normal mode, short page mode, extended operate mode, and register scratchpad mode.
Vector mode provides memory-to-memory vector instructions that operate on longer vectors, and, ironically, is one of the modes in which the short vector instructions are not available.
In extended operate mode, the short vector registers are also used to contain the matrices of bits used in the three bit matrix multiply instructions.
SU stands for the supplementary registers. These registers consist of a bank of 64 supplementary accumulator/index registers, and a bank of 64 supplementary floating-point registers.
These registers are used in vector register mode, to allow programs in that mode to perform a larger portion of their operations on a register-to-register basis, so that they might execute more rapidly. They constitute the scratchpad referred to in the name of this mode, which has nothing to do with the scratchpad registers, also used in this mode, but as additional base registers.
Note that the supplementary accumulator/index registers are 64 bits long rather than 32 bits long, to fully support 64-bit fixed-point operations. While 64-bit integer arithmetic is not particularly needed, the longer size of these registers is very useful in performing certain logical operations.
An asterisk in this column indicates that the bank of 64 supplementary floating-point registers can also be used in extended operate mode to supply additional bit matrix multiply registers for the BMM32 and BMM64 instructions.
LV stands for the long vector registers, and in addition to being used in used in vector register mode, they are also used in the two modes extended register scratchpad mode, and multi-way long vector register mode, which are closely similar, and in symmetric vector register mode and general register mode.
In the final column, N indicates that the operate instructions have the normal-mode form, A indicates that the operate instructions have the form for aligned instruction mode in which they are all 32 bits in length, and G indicates that the operate instructions have the form for general register mode. P indicates that the operate instructions all have a 16-bit prefix, as is done in advanced compound mode. When N* appears as an entry, this indicates that the operate instructions largely resemble those of normal mode, but are modified because addresses are changed in those modes. In vector register mode, there are 32 base registers provided, with the result that many instructions are lengthened in order to provide room for the longer base register field; this is indicated by an N* in the column.
In addition, there are fifteen other modes not shown above, described in a later section; these are the direct cache modes, which are identical to the fourteen of the sixteen 16-bit alignment modes, and one of the variant alignment modes, except that an additional block move instruction is defined for them, and addresses using base register 4 or greater (16 or greater for vector register mode and symmetric vector register mode) are instead interpreted as cache addresses.
The available modes will be fully described in the following sections: