The computer has two hundred and fifty-six possible codes indicating the set of instruction formats, or addressing modes, in use, or the instruction mode of the computer.
The first bit of the eight-bit field used to indicate the instruction mode indicates if a direct cache mode is used; in a direct cache mode, half the possible codes for base registers are instead used to supply additional address bits for an address within high-speed cache memory, used instead as a high-speed conventional memory under program control.
Each group of 128 instruction modes is further divided into two major parts, but these are not of equal size; 96 ordinary instruction modes, with instructions that are built from 16-bit parts, and observe 16-bit alignment, and 32 variant alignment modes which may be aligned on 32-bit boundaries, 8-bit boundaries, or possibly boundaries of areas of other sizes.
At this time, seventy-one of the codes in the first group of ninety-six have a defined meaning, and five of the thirty-two possible codes for variant alignment modes are defined.
Forty-two of the first group of sixty-seven defined addressing modes involve modifications to the form of an address, and these modifications will also apply to the addresses which appear in operate instructions; twenty-four of the other modes use the same form of operate instructions as used within normal mode, and five modes, advanced compound mode and four others deriving from it, in which the addresses are normally in the same format as normal mode, alters the format for the operate instructions by preceding most of them with a 16-bit prefix (short shift instructions are present in these modes, and another part of the opcode space is used to avoid an increase in the length of the jump instructions) in order to make them yield up more opcode space for the memory-reference instructions. In these modes, that 16-bit prefix is required also for the mode-independent instructions, rendering them no longer fully mode-independent.
The mode-independent instructions may also be no longer available from within a variant alignment mode, or at least are modified in form, and explicit indication of parallelism is also either not available or modified in form (although it is also true of the conventional stack modes that explicit indication of parallelism is not available for them, since for those modes, it would not be useful, as successive instructions are almost always logically dependent).
The number of possible operation modes defined here is, of course, excessive. It is intended to illustrate possible ways to make different tradeoffs within a limited opcode space, and also it grew as different ways were explored to make more optimized tradeoffs suitable to this particular architecture. A few of the operation modes other than normal mode, however, do have the practical usefulness of making important features of the architecture more readily available. The recent addition of alternate mode, and two related modes, appears to make it possible to dispense with a significant number of the instruction modes provided. The following limited set of modes: normal mode vector register mode full opcode alternate mode alternate mode semi-RISC mode as well as the direct cache versions of those modes, and in addition one variant alignment mode: general register mode appear to be sufficient. Vector register mode includes some vector operations not present in alternate mode (as well as the related full opcode alternate mode and semi-RISC mode), and general register mode is useful in emulation of architectures with more than eight general registers. Having alternate mode and semi-RISC mode in addition to full opcode alternate mode allows flexibility in address mode tradeoffs to what seems to be a sufficient extent as to make the other modes nearly superfluous. As one full opcode mode is included, and no modes with six-bit opcodes are in use, both the six-bit opcode translation and the seven-bit opcode translation features can be omitted as well. However, the bit field instructions in alternate mode and the two related modes do not include the possibility of conventional indexing with a 16-bit displacement rather than a 25-bit displacement. Thus, to include that feature as well, extended operate mode would need to be included as well, and that mode, having a six-bit opcode, makes retaining the opcode translation feature seem more attractive, although doing so is still not essential, given the presence of a full opcode mode. Note also that the complete absence of conventional indexing in alternate mode and full opcode alternate mode (but not semi-RISC mode) limits the usefulness of the direct cache versions of these modes. |
Although alternate mode does offer the possibility of a significant simplification of the instruction set architecture, having only one mode of operation, as is, after all, the conventional practice, is still to be preferred, and thus work continues on developing further improvements to the instruction format. Thus, Advanced Compound Mode has now been developed, the intent of which is to more closely match the length of instructions to their frequency of use. |
The chart below shows the codes for the sixty-five available instruction modes with 16-bit alignment and their names, and then the codes for the instruction modes with variant alignment followed by, in four major columns (the third being divided into four columns in its own right),
16-bit alignment: 0 000 0000: normal mode -- 65,536 SV N 0 000 0100: full opcode mode -- 65,536 SV SU LV N 0 000 0110: stack mode -- 65,536 SV N 0 000 0111: register stack mode -- 65,536 SV SU N 0 000 1000: extended operate mode -- 65,536/8,192 SV * N 0 000 1001: short shift mode -- 65,536 SV N 0 000 1011: full opcode short memory reference short shift mode -- 32,768 SV N*** 0 000 1110: condensed mode -- 65,536 SV N 0 000 1111: vector mode -- 65,536 SV N 0 001 0000: extended register short page mode B 4,096 *** SV SU N** 0 001 0001: extended register short page stack mode B 4,096 *** SV SU N** 0 001 0010: extended register short page extended operate mode B 4,096 *** SV SU N** 0 001 0011: extended register short page short shift mode B 4,096 *** SV SU N** 0 001 0100: extended short page full opcode mode B 4,096 *** SV N** 0 001 0101: extended short page short shift full opcode mode B 4,096 *** SV N** 0 001 0110: extended short page compact mode A,B 4,096 *** SV N** 0 001 0111: extended short page compact condensed mode B 4,096 *** SV N** 0 001 1000: symmetric address mode -- 65,536 SV N 0 001 1100: symmetric vector register mode 65,536* 65,536 * SV SU LV N* 0 010 0000: stateless scratchpad mode 64 65,536 SC SV N 0 010 0001: register scratchpad mode -- 65,536 SV SU N 0 010 0100: double base mode 256 32,768 S SV N 0 010 0101: flexible register mode -- 32,768/4,096 SV N 0 010 0111: simple compact mode -- 65,536 S SV SU N 0 010 1000: stateful scratchpad mode 512 65,536 SC SV N 0 010 1010: mutable scratchpad mode 512 65,536 SC SV N 0 010 1100: plain stateful scratchpad mode 512 65,536 SC SV N 0 010 1110: plain mutable scratchpad mode 512 65,536 SC SV N 0 011 0000: vector register mode 65,536* 65,536 * SV SU LV N* 0 011 0001: semi-RISC mode C 65,536** **** SV SU LV N**** 0 011 0010: alternate mode C 65,536** **** SV SU LV N**** 0 011 0011: full opcode alternate mode C 65,536** **** SV SU LV N**** 0 011 0100: comprehensive mode -- 65,536 SV * N 0 011 0110: universal mode C 65,536*** **** SV SU LV N**** 0 011 0111: register scratchpad universal mode C 65,536*** **** SV SU LV N**** 0 011 1000: advanced compound mode C 65,536**** **** SV SU LV P 0 011 1001: modified normal mode C 65,536**** **** SV SU LV P 0 011 1010: stack advanced compound mode C 65,536**** **** SV SU LV P 0 011 1011: large array mode C 65,536**** **** SV SU LV P 0 011 1100: short memory reference mode 32,768 65,536**** **** SV SU LV P 0 011 1101: alternate short memory reference mode 32,768 65,536**** **** SV SU LV P 0 011 1110: mixed operation mode C 65,536**** **** SV SU LV P 0 011 1111: pointer page mode C 65,536**** **** SV SU LV P 0 100 0000: register short page mode -- 4,096 SV SU N** 0 100 0001: register short page stack mode -- 4,096 SV SU N** 0 100 0010: register short page extended operate mode -- 4,096 SV SU N** 0 100 0011: register short page short shift mode -- 4,096 SV SU N** 0 100 0100: short page full opcode mode -- 4,096 SV N** 0 100 0101: short page short shift full opcode mode -- 4,096 SV N** 0 100 0110: short page compact mode A 4,096 ** SV N** 0 100 0111: short page compact condensed mode 4,096 SV N** 0 100 1000: short page mode 64 4,096 SC SV N** 0 100 1001: short page stack mode ** 4,096 ** SV N** 0 100 1010: short page extended operate mode 64 4,096 SC SV * N** 0 100 1011: short page short shift mode 64 4,096 SC SV N** 0 100 1100: stateful short page condensed mode 512 4,096 SC SV N** 0 100 1101: mutable short page condensed mode 512 4,096 SC SV N** 0 100 1110: plain stateful short page condensed mode 512 4,096 SC SV N** 0 100 1111: plain mutable short page condensed mode 512 4,096 SC SV N** 0 101 0000: selective register short page mode -- 32,768/4,096 SV SU N** 0 101 0001: selective register short page stack mode -- 32,768/4,096 SV SU N** 0 101 0010: selective register short page extended operate mode -- 32,768/4,096 SV SU N** 0 101 0011: selective register short page short shift mode -- 32,768/4,096 SV SU N** 0 101 0100: selective short page full opcode mode -- 32,768/4,096 SV N** 0 101 0101: selective short page short shift full opcode mode -- 32,768/4,096 SV N** 0 101 0110: selective short page compact mode A 32,768/4,096 ** SV N** 0 101 0111: selective short page compact condensed mode 32,768/4,096 SV N** 0 101 1000: selective short page mode 64 32,768/4,096 SC SV N** 0 101 1001: selective short page stack mode ** 32,768/4,096 ** SV N** 0 101 1010: selective short page extended operate mode 64 32,768/4,096 SC SV * N** 0 101 1011: selective short page short shift mode 64 32,768/4,096 SC SV N** 0 101 1100: selective stateful short page condensed mode 512 32,768/4,096 SC SV N** 0 101 1101: selective mutable short page condensed mode 512 32,768/4,096 SC SV N** 0 101 1110: selective plain stateful short page condensed mode 512 32,768/4,096 SC SV N** 0 101 1111: selective plain mutable short page condensed mode 512 32,768/4,096 SC SV N** Variant alignment: (32-bit) 0 110 0000: aligned instruction mode 64 32,768 SC A 0 110 0110: general register mode -- 16,777,216* SV SU LV G (8-bit) 0 111 1000: three-address RISC mode -- 32,768 **** 0 111 1100: flexible CISC mode 65,536* 65,536 * SU 0 111 1101: stack machine mode -- 65,536
Because the size of a displacement used in conjunction with the specification of a base register differs from one mode to another, when values are placed in the base registers for use, a decision is being made which may potentially limit the usefulness of some modes.
In particular, a program written to make use of another mode might find, if attempting to switch into short page mode for some instructions, that additional base registers would need to be allocated in order to make use of a specific address. Switching from short page mode to one of the other modes to make use of specific instructions does not encounter a similar limitation, since now the switch is being made to a mode with larger addresses.
In vector register mode, the number in the first column is indicating the number of bytes pointed to: the scratchpad registers are used as additional base registers, and the supplementary registers are used as a scratchpad that consists of registers, rather than one pointed to by registers.
In the case of stack mode, the scratchpad registers are used to point to single elements within an area of memory that is of arbitrary size, only determined by the amount of memory allocated for each of the eight stacks.
For short page compact mode, the scratchpad registers point to areas of memory 512 bytes in size; this is indicated by note A in this column; for the extended short page modes, the array scratchpad registers point to areas of memory 258,435,456 bytes in size (switching to this from a 4,096 byte page pointed to by the regular base registers being done within the instruction, instead of by the 32/28-bit addressing bit in the Program Status Block), and this is indicated by note B in this column. In universal mode, the scratchpad registers point to areas of memory 258,435,456 bytes in size, the pointer scratchpad registers point to areas of memory 65,536 halfwords in size, and the array scratchpad registers point to areas 4,096 words or 4,096 doublewords in size, indicated by note C in this column.
In the case of extended operate mode, the dual entry for the area of memory referenced by a given base register reflects the fact that in the bit field instructions, the address field of the instruction is taken to be a bit address, and thus covers a smaller expanse of memory.
The basic registers used in all modes except general register mode are the eight arithmetic/index registers, the eight base registers, and the eight floating-point registers. In general register mode, the supplementary registers are used for the functions of these registers, and thus the figure given for the size of the area to which a base register points, marked with an asterisk for this mode, indicates the size of the area to which a supplementary register points when used as a base register.
SC stands for the scratchpad registers. These are three additional banks of eight registers which are similar to the base registers. They are also used to point to the beginning of an area in memory, but that area is usually smaller than that which a base register points to.
In stateless scratchpad mode, stateful scratchpad mode, mutable scratchpad mode, and short page mode, these registers are used to make instructions possible that reference memory but which are only 16 bits long, by pointing to areas of memory within which items can be accessed with short addresses.
In simple compact mode and double base mode, only the first set of eight scratchpad registers are used; this is indicated by putting S instead of SC in this column.
The three banks of scratchpad registers are also used in register scratchpad mode, symmetric vector register mode, and multi-way long vector register mode, but in these modes they are merely used as additional base registers, increasing the number of base registers from 8 to 32. Thus, an asterisk is placed in this column for those modes. The scratchpad referred to in the name of this mode consists of the two groups of 64 supplementary registers.
The supplementary memory reference instructions can access the scratchpad registers in all modes, but no entries are placed in this column simply to reflect that fact.
In stack mode, the eight scratchpad registers are used as stack pointers, but the scratchpad pointer registers and the array scratchpad registers are not directly used, hence an entry of two asterisks appears at that point in the table. This is also done for the short page compact mode; in this mode, the eight scratchpad registers are used as base registers, pointing to pages 512 bytes in length, for 16-bit load/store instructions.
In the extended short page modes, three asterisks appear in this field, indicating that the array scratchpad registers are used as base registers for long pages, 258,435,456 bytes in length.
In universal mode, the scratchpad registers are used as base registers for long pages that contain arrays, 258,435,456 bytes in length, the pointer scratchpad registers are used as base registers for pages of program memory which, instead of being 65,536 bytes in length, are 65,536 halfwords in length, since all instructions begin on halfword boundaries, and the pointer scratchpad registers are only used as base registers in jump instructions, and the array scratchpad registers are used as base registers for short pages which only contain addresses; therefore, these pages, instead of being 4,096 bytes in length are 4,096 words in length, or 4,096 doublewords in length if 64-bit addressing is in effect, as the displacements in instructions are word or doubleword displacements. This is indicated by four asterisks in this column for that mode.
In alternate mode, full opcode alternate mode, and semi-RISC mode, as well as in advanced compound mode, the scratchpad registers are also used as base registers for areas of memory larger than indicated by the conventional base registers, but in this case of 33,554,432 bytes in length. As well, in advanced compound mode, the fixed-point supplementary registers can be used as base registers for areas of memory which are 524,288 bytes in length.
SV stands for the short vector registers. These are a bank of sixteen registers, each 256 bits in length, which can be treated as vectors of 32 bytes, 16 halfwords, 8 integers, or 4 long integers, as well as 8 floating-point numbers, 4 double-precision floating-point numbers, or 2 quad-precision floating-point numbers. They are used by instructions in normal mode, and in those modes where the available memory-reference addressing modes did not make it necessary to cut in half the opcode space available for the other instructions. Thus, they are used in normal mode, short page mode, extended operate mode, and register scratchpad mode.
Vector mode provides memory-to-memory vector instructions that operate on longer vectors, and, ironically, is one of the modes in which the short vector instructions are not available.
In extended operate mode, the short vector registers are also used to contain the matrices of bits used in the three bit matrix multiply instructions.
SU stands for the supplementary registers. These registers consist of a bank of 64 supplementary accumulator/index registers, and a bank of 64 supplementary floating-point registers.
These registers are used in vector register mode, to allow programs in that mode to perform a larger portion of their operations on a register-to-register basis, so that they might execute more rapidly. They constitute the scratchpad referred to in the name of this mode, which has nothing to do with the scratchpad registers, also used in this mode, but as additional base registers.
Note that the supplementary accumulator/index registers are 64 bits long rather than 32 bits long, to fully support 64-bit fixed-point operations. While 64-bit integer arithmetic is not particularly needed, the longer size of these registers is very useful in performing certain logical operations.
An asterisk in this column indicates that the bank of 64 supplementary floating-point registers can also be used in extended operate mode to supply additional bit matrix multiply registers for the BMM32 and BMM64 instructions.
LV stands for the long vector registers, and in addition to being used in used in vector register mode, they are also used in the two modes extended register scratchpad mode, and multi-way long vector register mode, which are closely similar, and in symmetric vector register mode and general register mode.
In the final column, N indicates that the operate instructions have the normal-mode form, A indicates that the operate instructions have the form for aligned instruction mode in which they are all 32 bits in length, and G indicates that the operate instructions have the form for general register mode. P indicates that the operate instructions all have a 16-bit prefix, as is done in advanced compound mode. When N*, N**, or N*** appears as an entry, this indicates that the operate instructions largely resemble those of normal mode, but are modified because addresses are changed in those modes. In short page mode, the 16-bit address fields contain an indirect bit and a three-bit base register field, moving the base register field out of the earlier part of the instruction, thus making extra opcode space available, and when this is done, N** appears in the column. In full opcode short memory reference short shift mode, the 16-bit address fields contain one bit to distinguish between normal memory-reference instructions and indexed memory reference instructions, and when this is done, N*** appears in the column. In vector register mode, there are 32 base registers provided, with the result that many instructions are lengthened in order to provide room for the longer base register field; this is indicated by an N* in the column. In universal mode, the field usually used for an index register is instead used to indicate an addressing mode, and the corresponding field used for a base register can be used for that purpose, or to indicate an index register; in that case, the base register field is moved to a location within the address field, and in that case N**** appears in the column.
In addition, there are ninteen other modes not shown above, described in a later section; these are the direct cache modes, which are identical to the nineteen 16-bit alignment modes, except that an additional block move instruction is defined for them, and addresses using base register 4 or greater (16 or greater for vector register mode and symmetric vector register mode) are instead interpreted as cache addresses.
Supplementary mode has its name in parentheses because this mode does not include opcodes for standard memory-reference instructions, and is not actually suitable on its own for program execution. It is intended to be used with the bimodal operation postfix supplementary bit feature to supply, in a single alternate mode, the additional instructions not available in normal mode or in the scratchpad modes.
In general, it is expected that a particular compiler will normally generate code for only one of the sixteen possible modes, the one best suited to the applications area that it supports, although the occasional use of the INWM instruction to access features from other modes is not cause for concern, and, in fact, may sometimes be almost a necessity, for example, in the case of using instructions from vector register mode for purposes of context switching when any scratchpad mode is used. However, a compiler intended to serve a very general set of requirements could include code generators for all eight modes, selectable by a command-line switch; this might be desirable with a C compiler, for example.
In a number of the modes of operation, some instruction formats will have, in order to conserve opcode space, a six-bit opcode field instead of a seven-bit opcode field. The correspondence between six-bit opcodes and seven-bit opcodes in effect is indicated by three bits in the Program Status Quadword, and the possible correspondences are thoroughly described in the section on the scratchpad modes, the first modes to be described using six-bit opcodes.
The symmetric address modes, the variant alignment modes, and the vector register mode are significantly different from the other available modes. Although the other modes can still be divided into two main groups, those using the regular operate instructions as used by normal mode, and those using the modified operate instructions as used by the scratchpad modes, they have much in common with each other, and simply provide a mechanism by which the programmer can choose the mode which contains those features that will actually be used by a given program. The chart below contains an overview of the features available in the various modes in this group:
Normal mode X X
Vector mode X X
Extended operate mode X X
Short shift mode X X
Short page mode X X
Short page extended operate mode X X
Short page short shift mode X X
Stateless scratchpad mode X X
Stateful scratchpad mode + X X
Stack mode X X
| | | | | | | |
64-bit integer, 48-bit and 128-bit floating point - | | | | | | |
Base registers point to 65,536 byte areas ------------ | | | | | |
Memory-to-memory vector instructions -------------------- | | | | |
Extended operate instructions ------------------------------ | | | |
16-bit long shift instructions -------------------------------- | | |
16-bit 64-element scratchpad memory-reference instructions ------- | |
16-bit 256-element scratchpad memory-reference instructions --------- |
16-bit instructions with three stack operations ------------------------
Thus, the choice of a mode involves a tradeoff between different features which provide either more compact code or extended processing power, and that through either additional instructions or more convenient access to larger areas of memory.
The asterisk in the column for 64-bit integer, 48-bit and 128-bit floating point for long scratchpad direct cache mode indicates that in that mode, all memory-reference instructions have only a five-bit opcode, so, while all types are accessible, using more than one fixed-point type and more than one floating-point type involves additional overhead; the plus sign in that column for stateful scratchpad mode indicates that in that mode, the scratchpad instructions have a four-bit opcode, limiting them, but not other instructions, to a limited set of types and/or operations without additional overhead.
In addition, one can combine normal mode and supplementary mode using the bimodal operation postfix supplementary bit feature, or one can use one of the short page modes along with setting the 32/28-bit displacement bit in the Program Status Block to replace the short 12-bit displacements in those instructions with 28-bit displacements, to obtain a larger combination of features than shown for any single mode in this table, and one can use an alternate correspondence between six-bit opcodes and seven-bit opcodes to obtain access to a different set of types with a six-bit opcode.
A large fraction of the instruction modes to be discussed in the sections that follow have been designed in attempts to reduce the amount of memory required for a given program.
Even the basic mode already described was designed with a view to improving code density.
The IBM 360 instruction set looked like this:
********DDDDSSSS ********DDDDXXXX BBBBaaaaaaaaaaaa
* = opcode, D = destination register, S = source register, X = index register, B = base register, a = address (or displacement).
The Motorola 68020 instruction set looked like this:
****DDD***...SSS ****DDD***...BBB aaaaaaaaaaaaaaaa ****DDD***...BBB .XXX....aaaaaaaa ****DDD***...BBB .XXX............ aaaaaaaaaaaaaaaa
where . = additional overhead or mode bits.
The format in the fourth line was added with the 68020. If one wished to use an index register with an address, the displacement shrank on the 68000. (The Philco 2000 apparently had this bizarre characteristic as well.)
In the architecture described here, as we have seen, I tried to combine the positive features of both architectures to achieve high code density, with the basic scheme:
*******DDDSSS... *******DDDXXXBBB aaaaaaaaaaaaaaaa
so that the architecture strongly resembled that of the 360, but by switching to groups of eight registers instead of groups of sixteen registers, to allow a more comfortable 64 K size for the area to which a base register points, instead of 4 K. (I follow the 360 in making the displacement unsigned; as it is signed on the 68000, the original Mac limited routines to 32K in size, using only the part after the address the base register points to.)
On the following pages, several modes with attempts at an even more compact instruction format will be encountered.
In the basic architecture, I used seven-bit opcodes to provide access to a wide range of basic data types, including 64-bit integers and 128-bit floating-point numbers. If I restricted myself to the three fixed-point types and two floating types of the original IBM 360, I could use a six-bit opcode, allowing me to use one bit in the instruction to switch to some additional special denser instruction format.
I did this in various ways. I found that the shift instruction, which was 32 bits long, could be reduced to 16 bits in length, if it was allowed to use as much opcode space as all the operate instructions. So one option was to use additional opcode space to make shift instructions shorter.
Instead of short shift instructions, the next choice offered in what follows is a mode that includes two register-to-register instructions in a single 16-bit halfword. The type is specified in advance, remaining constant over several instructions, so the opcode is four bits long. The destination register is always register zero, so the only other field in the instruction is a three-bit field indicating the source register.
One frustrating thing about the 360-like basic format I had used was that the index register field is usually zero most of the time, to indicate that no indexing is taking place; this meant that almost three bits were wasted in memory-reference instructions.
In order to recover three bits, I did have to make some sacrifices. So, I came up with one mode in which the opcode grew to eight bits, but indexed memory reference instructions could have only registers zero and one as their destinations - and only three registers could be index registers. (Setting the index register to zero indicated indirect addressing, since mode bits indicated conventional memory reference instructions which could have all eight destination registers.)
The formats in that mode were
..********DDDSSS ..********DDDBBB aaaaaaaaaaaaaaaa ..********DXXBBB aaaaaaaaaaaaaaaa
We then proceed to the page with my earliest attempts at a more condensed mode, the various scratchpad modes. Inspired by the PDP-8 and the Honeywell 316, I felt it ought to be possible to squeeze a memory-reference instruction (of a sort) instead of just a register-to-register instruction into a single 16-bit halfword.
Originally, to do this I modified the operate instructions extensively to cut the opcode space they used in half, but later I found a way to avoid this. The scratchpad modes now, in general, allow only four possible destination registers.
One family allows the use of scratchpad areas in memory with 64 entries, with the instruction formats
..DD******SSS... ..DD******XXXBBB aaaaaaaaaaaa ..DD******ssssss
where s = scratchpad source, and another family increased the size of the scratchpads to 256 elements by shrinking the opcodes of scratchpad instructions only from six bits to four. As with the two-instruction per word register to register format above, this depends on setting the type of instruction operands in advance, and it produces an instruction that resembles the single word memory-reference instructions of early 16-bit minicomputers. (Unlike later 16-bit minicomputers such as the PDP-11, of course, that used two words if recourse to memory was required for one of the operands, or three if both operands were in memory.)
On that page, I have added a recent attempt to achieve very compact code, the Simple Compact Mode, which combines several of the techniques seen thus far. The instruction formats in that mode are
....******DDDSSS ....******DDDBBB aaaaaaaaaaaa ...DDXX******BBB aaaaaaaaaaaa ..DD******ssssss
allowing an indexed memory reference instruction with four possible destination registers and three possible index registers, and in return gaining enough opcode space to permit both one type of scratchpad instruction and a 16-bit shift instruction.
Still further struggles to find an addressing mode which makes common instructions as compact as they are on simpler architectures with fewer addressing modes and fewer data types have led to Alternate Short Memory Reference Mode, with these instruction formats:
.******aaaaaaaaa ...*******DDDSSS ...*******DDDBBB .aaaaaaaaaaaa ...*******DDXXBB .aaaaaaaaaaaa
By trimming the address field to 15 bits, still long enough for me to find it satisfactory, and restricting indexed instructions to only four possible base, index, and destination registers, I manage to have, at least for the operations specifiable by a six-bit opcode, an instruction format that performs memory-reference instructions on a 512-byte area of memory in a single 16-bit halfword. Regular register-to-register and memory-reference instructions have an unrestricted seven-bit opcode, so despite making severe tradeoffs in some ways, the luxury of having unnormalized floating-point instructions given full priority is also enjoyed. (One could also give up that luxury to squeeze in the short branch instructions...)
Previously, to combine short shift instructions and scratchpad instructions, I resorted to a more extreme expedient to gain opcode space. Since the IBM 360 seemed to manage with having its base registers point only to 4K-byte regions, I moved the base register field from the first 16 bits of the instruction into the subsequent halfword containing the address.
Combining this with the various techniques elaborated upon in earlier pages yielded some modes which combined access to a wide range of features with the ability to code some operations quite compactly.
Another very early thing I attempted in the development of the architecture was to provide a mode in which a 16-bit word could contain three five-bit opcodes which indicated stack operations.
Under ideal circumstances, this could provide the ne plus ultra in code density. But for most pipelined implementations, it has the serious drawback that it basically mandates having successive instructions dependent on each other.
The historical development of the modes used here can be sketched as follows:
First, there was normal mode, attempting to provide a simple memory to register two-address CISC format with large contiguous memory pages.
Then, extended operate mode and short shift mode attempted to prove additional opcode space by removing less commonly-used data types from the repertoire of normal memory-reference instructions.
The short page mode attempted to allow more opcode space, to allow multiple features at the same time, by moving the base register field out to the 16-bit address constant, thus moving to shorter memory pages.
Vector register mode used a completely different instruction format, to permit an extensive tree of opcodes in order to support all the addressing modes needed for a computer with pipelined vector instructions, and vector registers like those of the Cray-1.
Then, numerous other modes experimented with various expedients, such as limiting the number of index registers, to obtain additional opcode space without shrinking the size of memory pages, such as comprehensive mode, universal mode, and alternate mode.
Most recently, at this time, advanced compound mode appears to have come closer to fulfilling the promise of alternate mode; by lengthening most of the operate instructions, opcode space has been made available for most of the desired features, including the provision of a relatively simple and orthogonal expression of the portion of the instruction set required for vector supercomputing.
The available modes will be fully described in the following sections: