A fourth group of instructions, with the prefix 173704, allows the computer to perform floating-point operations which allow a calculation to keep track of loss of significance. Also, because they behave, to an extent, like fixed-point operations, it is possible to define multiply extensibly and divide extensibly instructions acting on floating-point quantities by means of unnormalized arithmetic.
These instructions are only available when a compatible floating-point format is in effect. Suppression of the most significant bit of the mantissa and extremely gradual underflow or overflow preclude the use of unnormalized operations.
The opcodes for the instructions made available with this prefix are:
173704 010xxx SFMEUH Simple Floating Multiply Extensibly Unnormalized Halfword 173704 011xxx SFDEUH Simple Floating Divide Extensibly Unnormalized Halfword 173704 012xxx SFLUH Simple Floating Load Unnormalized Halfword 173704 013xxx SFSTUH Simple Floating Store Unnormalized Halfword 173704 014xxx SFAUH Simple Floating Add Unnormalized Halfword 173704 015xxx SFSUH Simple Floating Subtract Unnormalized Halfword 173704 016xxx SFMUH Simple Floating Multiply Unnormalized Halfword 173704 017xxx SFDUH Simple Floating Divide Unnormalized Halfword 173704 020xxx SFMEU Simple Floating Multiply Extensibly Unnormalized 173704 021xxx SFDEU Simple Floating Divide Extensibly Unnormalized 173704 022xxx SFLU Simple Floating Load Unnormalized 173704 023xxx SFSTU Simple Floating Store Unnormalized 173704 024xxx SFAU Simple Floating Add Unnormalized 173704 025xxx SFSU Simple Floating Subtract Unnormalized 173704 026xxx SFMU Simple Floating Multiply Unnormalized 173704 027xxx SFDU Simple Floating Divide Unnormalized 173704 030xxx SFMEUL Simple Floating Multiply Extensibly Unnormalized Long 173704 031xxx SFDEUL Simple Floating Divide Extensibly Unnormalized Long 173704 032xxx SFLUL Simple Floating Load Unnormalized Long 173704 033xxx SFSTUL Simple Floating Store Unnormalized Long 173704 034xxx SFAUL Simple Floating Add Unnormalized Long 173704 035xxx SFSUL Simple Floating Subtract Unnormalized Long 173704 036xxx SFMUL Simple Floating Multiply Unnormalized Long 173704 037xxx SFDUL Simple Floating Divide Unnormalized Long 173704 042xxx LUMDE Load Unnormalized Medium Decimal Exponent 173704 043xxx STUMDE Store Unnormalized Medium Decimal Exponent 173704 044xxx AUMDE Add Unnormalized Medium Decimal Exponent 173704 045xxx SUMDE Subtract Unnormalized Medium Decimal Exponent 173704 046xxx MUMDE Multiply Unnormalized Medium Decimal Exponent 173704 047xxx DUMDE Divide Unnormalized Medium Decimal Exponent 173704 062xxx LUDDE Load Unnormalized Double Decimal Exponent 173704 063xxx STUDDE Store Unnormalized Double Decimal Exponent 173704 064xxx AUDDE Add Unnormalized Double Decimal Exponent 173704 065xxx SUDDE Subtract Unnormalized Double Decimal Exponent 173704 066xxx MUDDE Multiply Unnormalized Double Decimal Exponent 173704 067xxx DUDDE Divide Unnormalized Double Decimal Exponent 173704 100xxx MEUM Multiply Extensibly Unnormalized Medium 173704 101xxx DEUM Divide Extensibly Unnormalized Medium 173704 102xxx LUM Load Unnormalized Medium 173704 103xxx STUM Store Unnormalized Medium 173704 104xxx AUM Add Unnormalized Medium 173704 105xxx SUM Subtract Unnormalized Medium 173704 106xxx MUM Multiply Unnormalized Medium 173704 107xxx DUM Divide Unnormalized Medium 173704 110xxx MEU Multiply Extensibly Unnormalized 173704 111xxx DEU Divide Extensibly Unnormalized 173704 112xxx LU Load Unnormalized 173704 113xxx STU Store Unnormalized 173704 114xxx AU Add Unnormalized 173704 115xxx SU Subtract Unnormalized 173704 116xxx MU Multiply Unnormalized 173704 117xxx DU Divide Unnormalized 173704 120xxx MEUD Multiply Extensibly Unnormalized Double 173704 121xxx DEUD Divide Extensibly Unnormalized Double 173704 122xxx LUD Load Unnormalized Double 173704 123xxx STUD Store Unnormalized Double 173704 124xxx AUD Add Unnormalized Double 173704 125xxx SUD Subtract Unnormalized Double 173704 126xxx MUD Multiply Unnormalized Double 173704 127xxx DUD Divide Unnormalized Double 173704 130xxx MEUQ Multiply Extensibly Unnormalized Quad 173704 131xxx DEUQ Divide Extensibly Unnormalized Quad 173704 132xxx LUQ Load Unnormalized Quad 173704 133xxx STUQ Store Unnormalized Quad 173704 134xxx AUQ Add Unnormalized Quad 173704 135xxx SUQ Subtract Unnormalized Quad 173704 136xxx MUQ Multiply Unnormalized Quad 173704 137xxx DUQ Divide Unnormalized Quad
Note that, since the decimal exponent operations still involve a mantissa in binary form, and a partial digit is present at the end of numbers in both of these formats, the difference between the exponents of the high and low portions of a compound floating-point number would not be an integer, even if the low portion extended the mantissa with additional decimal digits instead of continuing on as a portion of a purely binary mantissa. Therefore the multiply extensibly and divide extensibly operations are not provided for this type, as there exists no appropriate way to define them.
Unnormalized add or subtract instructions operate by first aligning the operand with the lower exponent with the other operand, and then performing the addition or subtraction on the mantissa portion of the arguments. If a carry out of the mantissa results, a single right shift, with adjustment of the exponent, is performed; otherwise, no repositioning of the mantissa is performed.
Unnormalized multiply or divide instructions produce a result which has either as many leading zeroes as or one less leading zero than that of the operand with the greater number of leading zeroes, so as to correctly indicate the significance of the result. The number of leading zeroes will be the same if the mantissa of the result is equal to or greater than the mantissa of the operand with the greater number of leading zeroes (in the case where both operands have the same number of leading zeroes, if the mantissa of the operand is equal to or greater than the mantissas of both operands), and it will be one less otherwise. Thus, these instructions, unlike the unnormalized add and subtract instructions, do not work by merely omitting a postnormalization step; instead, they are specifically designed to support significance arithmetic.
Significance arithmetic is one method of allowing a computer to keep track of ongoing errors in a calculation. Other methods of doing this are also available, significance arithmetic is considered by some to be flawed, and at least one of the other methods of doing this, interval arithmetic, tends to be acknowledged as having a somewhat greater degree of mathematical validity than significance arithmetic, although it, too, is considered to be of limited benefit rather than approaching the effectiveness of a panacea in this area. Despite the fact that these concerns have some validity, the simple form of significance arithmetic that can be obtained through unnormalized arithmetic is considerably more amenable to a hardware implementation than most other possible methods. The IBM 7030, or STRETCH, had an option of adding a constant value, termed a noise value, to the last bits of floating-point numbers; thus, this option was equivalent to the method, available today on IEEE-754-compliant systems today of running the same program with different rounding modes selected, although it resembles a different proposed method, of appending random noise bits to the ends of floating-point numbers. The major limitation of significance arithmetic is that it will indicate when precision is lost in an individual step of a calculation, but it will not indicate how error accumulates due to the involvement of a large number of quantities of limited accuracy in a calculation. This limitation is not entirely a bad thing, as it does not prevent significance arithmetic from pointing out correctable deficiencies in programs, while still permitting that form of arithmetic to be used even with computations such as simulations, from which useful data can be obtained, even though the final "result", in the sense of the state of the system, is nonsense. That is, a simulation of the Earth's atmosphere can still be used to learn general facts about how different types of weather systems behave, even if it is allowed to run past the amount of simulated time for which it could, if loaded with the actual present state of the Earth's atmosphere, yield accurate weather forecasts. (A full discussion of chaos theory is beyond the scope of this section.) |
Note that there is one circumstance under which an unnormalized arithmetic instruction will not retain significance, but will instead post-normalize despite the fact that this will indicate the presence of nonexistent significance in this number: that is when the result is near the upper end of the valid exponent range, and an unnormalized result would lead to exponent overflow.
The unnormalized multiply extensibly and divide extensibly instructions behave like the analogous operations on integers, where the mantissa portions of the arguments are the integers, and the exponents are adjusted so as to indicate the numerical magnitude of the result. Where numbers occupying a pair of registers are generated, both have an exponent part, and the difference between the two exponents reflects the precision of the floating-point type in use. Fixed-point overflow of the exponent is allowed and ignored, and, where a special value of the exponent is used to indicate symbols representing "not-a-number" (NaN) values, that value is skipped.
Unlike the integer multiply extensibly and divide extensibly instructions, their operands always consist of multiple registers at the given precision; a double-length operand is never a single register at a higher precision. Thus, these instructions always behave like Multiply Extensibly and Divide Extensibly, never like Multiply Extensibly Halfword and Divide Extensibly Halfword, even when the basic type does not have the full 128-bit length of a floating-point register.
In an unnormalized multiply extensibly instruction, if the destination is in register N, the product is in registers N and N+1; register N+1 contains an exponent equal to the sum of the exponents of the arguments, and register N has an adjusted exponent which may be incorrect if a fixed-point overflow took place.
In an unnormalized divide extensibly instruction, when the destination field of the instruction specifies register N, the dividend is in register N and N+1, and the exponent in register N is the one considered as being valid; after the operation, registers N and N+1 contain the quotient, which is not rounded, unlike the result of a regular unnormalized divide instruction, and register N+2 contains the remainder.
It is these instructions, rather than the simple multiply unnormalized and divide unnormalized instructions, that work by omitting postnormalization, because their purpose is to facilitate software multi-precision floating-point operations.
The Multiply Extensibly Unnormalized and Divide Extensibly Unnormalized instructions are unavailable, even though the other unnormalized operations are available, with the Modified Comprehensive, Modified Standard, and Modified Native formats. However, if neither Extremely Gradual Underflow nor Extremely Gradual Overflow is enabled, they are available, along with the other unnormalized operations, for the Native format, and if these features, and Hyper-Gradual Overflow and Hyper-Gradual Underflow as well are all turned off, they are also available, along with the other unnormalized operations, for the Comprehensive format.
Note that there are no unnormalized single-operand instructions. Dividing a number by itself will provide a one with the same number of significant digits as the original number, and this can be multiplied by the result of a conventional single-operand instruction to produce a result with the desired significance. This technique is, however, not applicable to all the single-operand instrcutions; the logarithm function is an obvious case where a special rule applies to the number of significant bits in the logarithm of a number with a given number of significant bits.
An additional group of instructions in this prefix facilitates working with unnormalized numbers that encode significance:
173704 142xxx LUAIM Load Unnormalized as Interval Medium 173704 143xxx SIAUM Store Interval as Unnormalized Medium 173704 146xxx LUAIMDE Load Unnormalized as Interval Medium Decimal Exponent 173704 147xxx SIAUMDE Store Interval as Unnormalized Medium Decimal Exponent 173704 152xxx LUAI Load Unnormalized as Interval 173704 153xxx SIAU Store Interval as Unnormalized 173704 154xxx SFLUAIH Simple Floating Load Unnormalized as Interval Halfword 173704 155xxx SFSIAUH Simple Floating Store Interval as Unnormalized Halfword 173704 162xxx LUAID Load Unnormalized as Interval Double 173704 163xxx SIAUD Store Interval as Unnormalized Double 173704 164xxx SFLUAI Simple Floating Load Unnormalized as Interval 173704 165xxx SFSIAU Simple Floating Store Interval as Unnormalized 173704 166xxx LUAIDDE Load Unnormalized as Interval Double Decimal Exponent 173704 167xxx SIAUDDE Store Interval as Unnormalized Double Decimal Exponent 173704 172xxx LUAIQ Load Unnormalized as Interval Quad 173704 173xxx SIAUQ Store Interval as Unnormalized Quad 173704 174xxx SFLUAIL Simple Floating Load Unnormalized as Interval Long 173704 175xxx SFSIAUL Simple Floating Store Interval as Unnormalized Long
These instructions convert between an unnormalized number, which may be in a register or in storage, and a pair of numbers in consecutive registers the first of which is an even-numbered register. The LUAI instructions load the first register with the unnormalized number normalized by padding it with zeroes, and the second register with the unnormalized number normalized and padded on the right with ones. The SIAU instructions attempt to find the unnormalized number which most tightly includes the two numbers in the two registers that are the destination operand of the instruction to store in the source operand. If the two components of the destination operand being converted and stored have the same sign, the one that has the lowest magnitude (the lowest absolute value) must be in the lower numbered register.
The prefix 173705 is used for a related set of modified floating point operations, applicable only to the decimal exponent types.
173705 044xxx AMDEH Add Medium Decimal Exponent Humanized 173705 045xxx SMDEH Subtract Medium Decimal Exponent Humanized 173705 046xxx MMDEH Multiply Medium Decimal Exponent Humanized 173705 047xxx DMDEH Divide Medium Decimal Exponent Humanized 173705 064xxx ADDEH Add Double Decimal Exponent Humanized 173705 065xxx SDDEH Subtract Double Decimal Exponent Humanized 173705 066xxx MDDEH Multiply Double Decimal Exponent Humanized 173705 067xxx DDDEH Divide Double Decimal Exponent Humanized
These operations also accept unnormalized numbers as operands, and may produce unnormalized results, but they do so based on a different criterion from the conventional unnormalized instructions described above.
The divide instructons always produce a normalized result, but they explicitly accept unnormalized inputs without creating an exception.
The multiply instructions produce a result having the same number of significant digits (where possible) as there would be digits in the product of the mantissas of the two operands, where these mantissas are treated as decimal integers.
The add and subtract instructions produce a result that includes, as its least significant digit, a digit having the same place value as the lesser of the place values of the least significant digits of the two operands.
When two numbers are added together using an unnormalized operation, they are brought into alignment, and digit positions not part of either operand originally before alignment are omitted from the result; with a humanized operation, only digits not part of both operands originally before alignment are omitted from the result.
These rules correspond to the "ideal exponent" rules used with the new Decimal Floating Point architecture to be specified in the revised version of the IEEE 754 standard, and implemented in the IBM z9 computer.